Configurable storage blocks having simple first-in first-out enabling circuitry
An integrated circuit may have configurable storage blocks. A configurable storage block may include a memory array, and arithmetic and control circuitry. The arithmetic and control circuitry may be used to determine whether to operate the configurable storage block in a first mode which may provide random access to the memory array or in a second mode which may provide access to the memory array in a predefined order. Thus, the configurable storage block may implement simple first-in first-out modules and shift registers in addition to implementing memory modules with random access. Arithmetic and control circuitry may include a multiplexer that determines whether the configurable storage block is implementing simple first-in first-out modules or shift registers. When the configurable storage block implements first-in first-out modules, an up-down counter may be activated to generate a count value received at the multiplexer.
1. A configurable storage circuit, comprising:
a memory array;
a write address generation circuit that generates a write address for accessing the memory array; and
a control circuit that receives a length value and that generates a read address for accessing the memory array based on the received length value, wherein the write address and the read address are separated by a fixed amount while the configurable storage circuit is configured in a shift register mode, and wherein the fixed amount is equal to one less than the length value while the configurable storage circuit is configured in the shift register mode.
2. The configurable storage circuit of claim 1 , wherein the write address and the read address are separated by a variable amount while the configurable storage circuit is configured in a first-in first-out (FIFO) mode.
3. The configurable storage circuit of claim 2 , wherein the variable amount is equal to one less than a number of data entries currently stored in the memory array while the configurable storage circuit is configured in the first-in first-out (FIFO) mode.
4. The configurable storage circuit of claim 1 , wherein the control circuit includes a multiplexing circuit.
5. A configurable storage circuit, comprising:
a memory array;
a write address generation circuit that generates a write address for accessing the memory array; and
a control circuit that receives a value and that generates a read address for accessing the memory array based on the received value, wherein the control circuit includes a multiplexing circuit, wherein the control circuit further includes a counter of a first type, wherein the write address generation circuit includes a counter of a second type that is different than the first type, and wherein, in a shift register mode, the write address and the read address are separated by a fixed amount that is equal to one less than the value.
6. The configurable storage circuit of claim 5 , wherein the counter in the control circuit comprises an up-down counter.
7. The configurable storage circuit of claim 6 , wherein the multiplexing circuit has a first input that directly receives the value and a second input that receives a count value from the up-down counter.
8. The configurable storage circuit of claim 7 , wherein the control circuit receives a write enable signal and a read enable signal, and wherein the up-down counter counts in a first direction when only the write enable signal is asserted and counts in a second direction that is different than the first direction when only the read enable signal is asserted.
9. A method of operating a configurable storage circuit, comprising:
with a write address generator in the configurable storage circuit, generating a write address;
with a control circuit in the configurable storage circuit, receiving a value and generating a corresponding count value based on the value;
operating the configurable storage circuit in a first-in first-out mode by selectively adjusting the count value;
computing a read address based on the write address and the count value; and
accessing a memory array in the configurable storage circuit using the write address and the read address.
10. The method of claim 9 , further comprising:
operating the configurable storage circuit in a shift register mode by setting the count value equal to the received value.
11. The method of claim 9 , wherein generating the count value comprises using an up-down counter to count up in response to only writing into the memory array and to count down in response to only reading from the memory array.
12. The method of claim 11 , wherein the control circuit includes a multiplexer with a first input, a second input, and an output, the method further comprising:
with the multiplexer, receiving the value at its first input, receiving the count value at its second input, outputting the value at its output when the configurable storage circuit is operated in a first mode, and outputting the count value at its output when the configurable storage circuit is operated in the first-in first-out mode.