Logic circuits with simultaneous dual function capability
Integrated circuits with programmable logic regions are provided. The programmable logic regions may be organized into smaller logic units sometimes referred to as a logic element. A logic element may include four lookup tables coupled to an adder carry chain. At least some of the lookup tables are configured to output combinatorial outputs, whereas the adder carry chain are used to output sum outputs. Both the combinatorial outputs and the sum outputs may be used simultaneously to support a multiplication operation, three or more logic operations, or arithmetic and combinatorial operations in parallel.
1. An integrated circuit, comprising:
a logic element that comprises:
a first lookup table configured to directly generate a combinatorial function output;
a second lookup table configured to generate an anti-function output that complements the combinatorial function output; and
an adder configured to combine the combinatorial function output generated by the first lookup table with the anti-function output generated by the second lookup table to produce a corresponding arithmetic function output, wherein the combinatorial function output and the arithmetic function output are simultaneously active.
2. The integrated circuit of claim 1 , wherein the logic element further comprises:
a third lookup table configured to directly generate an additional combinatorial function output;
a fourth lookup table configured to configured to generate an additional anti-function output that complements the additional combinatorial function output; and
an additional adder configured to combine the additional combinatorial function output generated by the third lookup table with the additional anti-function output generated by the fourth lookup table to produce an additional arithmetic function output.
3. The integrated circuit of claim 2 , wherein the logic element is configured to multiply a first two-bit input signal by a second two-bit input signal.
4. The integrated circuit of claim 2 , wherein the additional combinatorial function output and the additional arithmetic function output are simultaneously active with the combinatorial function output and the arithmetic function output, and wherein the adder is configured to receive a carry signal from the additional adder.
5. The integrated circuit of claim 1 , wherein the logic element is configured to support more than two combinatorial functions.
6. The integrated circuit of claim 5 , wherein the logic element further comprises:
a third lookup table configured to directly generate an additional combinatorial function output;
a fourth lookup table configured to configured to output zero; and
an additional adder configured to combine the additional combinatorial function output generated by the third lookup table with the zero generated by the fourth lookup table to produce a carry signal that is fed to the adder.
7. The integrated circuit of claim 6 , wherein the combinatorial function output, the additional combinatorial function output, and the arithmetic function output comprise at least three different exclusive-OR function outputs.
8. The integrated circuit of claim 1 , further comprising:
a first additional logic element; and
a second additional logic element, wherein the first and second additional logic elements are coupled in a chain.
9. The integrated circuit of claim 8 , wherein the logic element, the first additional logic element, and the second additional logic element are configured to multiply a first three-bit input signal by a second three-bit input signal.
10. The integrated circuit of claim 8 , wherein the first additional logic element comprises an additional lookup table configured to generate an additional combinatorial function output that is fed back as an input to at least one other lookup table within either the logic element, the first additional logic element, or the second additional logic element.
11. An integrated circuit, comprising:
a logic element that comprises:
a first lookup table;
a second lookup table;
a third lookup table;
a fourth lookup table;
a first output on which a first combinatorial function output is generated using signals produced by at least one of the first and second lookup tables;
a second output on which a second combinatorial function output is generated using signals produced by at least one of the third and fourth lookup tables; and
a third output on which a third combinatorial function output is generated using signals produced by at least one of the first, second, third, and fourth lookup tables.
12. The integrated circuit of claim 11 , wherein the first, second, third, and fourth lookup tables are all configured to support the same logic function.
13. The integrated circuit of claim 11 , wherein the first, second, third, and fourth lookup tables are configured to receive a plurality of input signals, and wherein the logic element further comprises multiplexing circuitry configured to receive additional input signals other than the plurality of input signals.
14. The integrated circuit of claim 13 , wherein the multiplexing circuitry comprises:
a first multiplexer configured to receive signals from the first and second lookup tables and to generate the first combinatorial function output, wherein the first multiplexer is controlled by a first input signal in the additional input signals; and
a second multiplexer configured to receive signals from the third and fourth lookup tables and to generate the second combinatorial function output, wherein the second multiplexer is controlled by a second input signal in the additional input signals.
15. The integrated circuit of claim 14 , wherein the multiplexing circuitry further comprises:
a third multiplexer configured to receive signals from the first and second multiplexers and to generate the third combinatorial function output, wherein the third multiplexer is controlled by the first input signal in the additional input signals.
16. An integrated circuit, comprising:
a logic element that comprises:
a plurality of lookup tables; and
an adder carry chain configured to receive signals from the plurality of lookup tables and further configured to simultaneously generate an arithmetic function output and a combinatorial function output, wherein the adder carry chain comprises logic XOR gates configured to generate output bits for the arithmetic function output.
17. The integrated circuit of claim 16 , wherein the plurality of lookup tables comprises:
a first lookup table configured as a first logic function;
a second lookup table configured as a second logic function;
a third lookup table configured as the first logic function; and
a fourth lookup table configured as the second logic function.
18. The integrated circuit of claim 17 , wherein the first logic function is a logic XOR function, and wherein the second logic function is a logic AND function.
19. The integrated circuit of claim 16 , wherein a subset of the plurality of lookup tables within the logic element is configured to directly generate output bits for the combinatorial function output.