Reticle stitching to achieve high-capacity integrated circuit
A reticle-stitched integrated circuit is provided. The reticle-stitched integrated circuit extends over a first die area and a second die area of an integrated circuit wafer. While individually the first die area and the second die area are within their respective reticle limits, collectively the first die area and the second die area exceed the reticle limit. A first layer of the reticle-stitched integrated circuit may have communication wires that remain exclusively in only one of the first die area and the second die area. A second layer of the reticle-stitched integrated circuit may have communication wires that overlap the first die area and the second die area, thereby allowing communication between the two die areas and enabling the reticle-stitched integrated circuit to exceed the limit of the reticle.
1 . A reticle-stitched integrated circuit device extending over a first die area within a reticle limit of a first area of an integrated circuit wafer from which the integrated circuit device is patterned and a second die area within a reticle limit of a second area of the integrated circuit wafer, the integrated circuit device comprising:
a first layer comprising communication wires in the first die area and the second die area, wherein all communication wires of the first layer that are located in the first die area are exclusively within the first die area and all communication wires of the first layer that are located in the second die area are exclusively within the second die area; and
a second layer comprising communication wires in the first die area and the second die area, wherein at least some communication wires of the second layer that are located in the first die area overlap with at least some communication wires of the second layer that are located in the second die area.
2 . The integrated circuit device of claim 1 , wherein the communication wires of the first layer are shorter than the communication wires of the second layer.
3 . The integrated circuit device of claim 1 , comprising a first plurality of layers that includes the first layer, wherein the first plurality of layers comprise communication wires in the first die area and the second die area, wherein all communication wires of the first plurality of layers that are located in the first die area are exclusively within the first die area and all communication wires of the first plurality of layers that are located in the second die area are exclusively within the second die area.
4 . The integrated circuit device of claim 3 , wherein the first plurality of layers is disposed beneath the second layer.
5 . The integrated circuit device of claim 1 , comprising a second plurality of layers that includes the second layer, wherein the second plurality of layers comprise communication wires in the first die area and the second die area, wherein at least some communication wires of the second plurality of layers that are located in the first die area overlap with at least some communication wires of the second plurality layers that are located in the second die area.
6 . The integrated circuit device of claim 1 , wherein the communication wires of the first layer have a uniform pattern in the first die area and in the second die area.
7 . The integrated circuit device of claim 1 , wherein a first pattern of the communication wires of the first die area in the second layer is different from a second pattern of the communication wires of the second die area in the second layer.
8 . The integrated circuit device of claim 1 , wherein:
the first layer comprises communication wires in a third die area located within a reticle limit of a third area of the integrated circuit wafer from which the integrated circuit device is patterned, wherein all communication wires of the first layer that are located in the third die area are exclusively within the third die area; and
the second layer comprises communication wires in the third die area, wherein at least some communication wires of the second layer that are located in the third die area overlap with at least some communication wires of the second layer that are located in the second die area or at least some communication wires of the second layer that are located in the first die area.
9 . The integrated circuit device of claim 8 , wherein the third die area is adjacent to the first die area.
10 . The integrated circuit device of claim 8 , wherein the third die area is adjacent to the second die area but not the first die area.
11 . The integrated circuit device of claim 8 , wherein at least some of the communication wires of the second layer that are located in the third die area overlap with at least some of the communication wires of the second layer that are located in the second die area and at least some communication wires of the second layer that are located in the first die area.
12 . An integrated circuit device comprising:
a first die area disposed within a first reticle limit of a first area of an integrated circuit wafer from which the integrated circuit device is formed; and
a second die area disposed within a second reticle limit of a second area of the integrated circuit wafer from which the integrated circuit device is formed;
wherein:
the first die area and the second die area comprise a first plurality of layers having a respective first plurality of patterns, wherein the first plurality of patterns remain entirely within the first die area and within the second die area; and
the first die area and the second die area comprise a second plurality of layers having a respective second plurality of patterns, wherein at least some of the second plurality of patterns overlap in a boundary area between the first die area and within the second die area.
13 . The integrated circuit device of claim 12 , wherein the first die area and the second die area of the first plurality of layers are adjacent and at least some of the second plurality of patterns overlap between one edge of the first die area and one edge of the second die area.
14 . The integrated circuit device of claim 12 , wherein the first plurality of layers are below a threshold layer and the second plurality of layers are above the threshold layer.
15 . The integrated circuit device of claim 12 , wherein the second plurality of patterns comprise a size of the first die area that is different from a size of the second die area.
16 . The integrated circuit device of claim 12 , wherein at least one edge of the first die area and the second die area comprise at least one interconnection resource for signal transfer or off-die communication.
17 . The integrated circuit device of claim 16 , wherein the second plurality of layers comprise communication wires connecting from interconnect resources along an edge of the first die area to interconnect resources along an edge of the second die area.
18 . The integrated circuit device of claim 12 , wherein the first plurality of patterns comprise a first pattern comprising at least one sacrificial edge in the first die area that includes unused components of die-to-die interconnect resources.
19 . The integrated circuit device of claim 18 , wherein the sacrificial edge is adjacent to a second sacrificial edge in the second die area at a boundary area.