Systems and methods for tracking synthesis optimizations for circuit designs
A method is provided for using an integrated circuit design tool to optimize a circuit design for an integrated circuit. Optimizations that affect first circuits in the circuit design and that are performed during synthesis of the circuit design for the integrated circuit are recorded in first records in a database. Second records are recorded in the database that indicate second circuits in the circuit design that fanin to or fanout from the first circuits and that are affected by the optimizations. A root cause of at least one of the optimizations is determined using the first and the second records in the database. A sequence of the optimizations affecting the first and the second circuits is determined using the first and the second records in the database.
1 . A method of using an integrated circuit design tool to optimize a circuit design for an integrated circuit, the method comprising:
recording optimizations of first circuits in the circuit design in first records in a database that are performed during synthesis of the circuit design for the integrated circuit;
creating second records in the database that indicate second circuits in the circuit design that fanin to or fanout from the first circuits and that are affected by the optimizations;
determining a root cause of at least one of the optimizations using the first records and the second records in the database;
determining a sequence of the optimizations affecting the first circuits and the second circuits using the first records and the second records in the database;
sweeping each instance of logic circuits in a hierarchy in the circuit design; and
providing first data for a table to be presented in a user interface comprising the hierarchy of instances of the logic circuits that indicates how many of the first circuits in each of the instances were optimized away during the synthesis.
2 . The method of claim 1 , wherein the hierarchy comprises sub-hierarchies.
3 . The method of claim 1 , wherein recording the optimizations of the first circuits in the circuit design further comprises:
recording the first circuits in the circuit design that have been removed during the synthesis in the first records.
4 . The method of claim 3 , wherein the first circuits in the circuit design that have been removed during the synthesis have terminals stuck at constant values, function as wires, or have lost fanouts.
5 . The method of claim 1 further comprising:
generating tables that indicate connections between the first circuits and the second circuits; and
filtering between the tables to identify the first and the second circuits in the circuit design that have been optimized away during the synthesis.
6 . The method of claim 1 further comprising:
providing hierarchy statistics on a size and a percentage of the circuit design that is affected by the optimizations.
7 . The method of claim 1 further comprising:
providing second data to display a circuit schematic of the first circuits and the second circuits that are affected by the optimizations.
8 . The method of claim 1 further comprising:
recording additional optimizations of at least a subset of the second circuits in the circuit design performed during the synthesis in third records in the database; and
creating fourth records in the database that indicate third circuits in the circuit design that fanin to or fanout from the subset of the second circuits and that are affected by the additional optimizations.
9 . The method of claim 1 further comprising:
providing second data for the user interface that indicate the sequence of the optimizations affecting the first circuits and the second circuits and the root cause using the first records and the second records in the database.
10 . A non-transitory computer-readable storage medium comprising instructions stored thereon for causing a computer to execute a method for optimizing a circuit design for an integrated circuit using a design tool, the method comprising:
storing optimizations that remove first circuits in the circuit design during synthesis of the circuit design for the integrated circuit in first records in a database;
storing second records in the database that indicate second circuits in the circuit design that fanin to or fanout from the first circuits, wherein functions of the second circuits are affected by the optimizations;
sweeping each instance of logic circuits in a hierarchy in the circuit design; and
providing first data for a user interface that indicate a root cause of one of the optimizations affecting the first circuits and the second circuits and a sequence of the optimizations affecting the first circuits and the second circuits using the first records and the second records stored in the database, wherein the first data comprises the hierarchy of instances of the logic circuits in the circuit design that indicates how many of the first circuits in each of the instances were removed during the synthesis.
11 . The non-transitory computer-readable storage medium of claim 10 , wherein providing the first data for the user interface further comprises:
generating tables that indicate connections in the circuit design between the first circuits and the second circuits; and
filtering between the tables to identify portions of the circuit design that have been optimized away during the synthesis.
12 . The non-transitory computer-readable storage medium of claim 10 , wherein
sweeping each instance of the logic circuits in the hierarchy in the circuit design further comprises sweeping into all instances of a module in the circuit design, and wherein the module is a group of the logic circuits that is repeated in the instances of the module in the circuit design.
13 . The non-transitory computer-readable storage medium of claim 10 , wherein providing the first data for the user interface further comprises:
providing second data to display a circuit schematic of the first circuits and the second circuits that are affected by the optimizations.
14 . The non-transitory computer-readable storage medium of claim 10 further comprising:
storing additional optimizations that remove at least a subset of the second circuits in the circuit design during the synthesis in third records in the database.
15 . The non-transitory computer-readable storage medium of claim 10 , wherein storing the optimizations that remove the first circuits in the circuit design further comprises:
storing the optimizations from a hierarchical, folded netlist that represents the circuit design, wherein the first circuits and the second circuits are in multiple hierarchies in the netlist.
16 . A circuit design system configured to implement a circuit design tool for optimizing a circuit design for an integrated circuit, wherein the circuit design system comprises:
logic synthesis and optimization tools that perform optimizations of first circuits in the circuit design during synthesis of the circuit design for the integrated circuit and that store the optimizations as first records in a database;
wherein the logic synthesis and optimization tools store second records in the database that identify second circuits in the circuit design that fanin to the first circuits and that are affected by the optimizations;
wherein the logic synthesis and optimization tools store third records in the database that identify third circuits in the circuit design that fanout from the first circuits and that are affected by the optimizations,
wherein the logic synthesis and optimization tools provide first data for a user interface that indicate a sequence of the optimizations affecting the first circuits, the second circuits, and the third circuits using the first records, the second records, and the third records stored in the database, and
wherein the logic synthesis and optimization tools sweep each instance of logic circuits in a hierarchy in the circuit design and provide second data for the user interface comprising the hierarchy of instances of the logic circuits that indicates how many of the first circuits in each of the instances were removed during the synthesis.
17 . The circuit design system of claim 16 , wherein the logic synthesis and optimization tools sweep into all instances of a module in the circuit design, and wherein the module is a group of the logic circuits that is repeated in the instances of the module in the circuit design.
18 . The circuit design system of claim 16 , wherein the logic synthesis and optimization tools remove the first circuits in the circuit design during the synthesis and store removal of the first circuits as the first records.
19 . The circuit design system of claim 16 , wherein the logic synthesis and optimization tools generate tables that indicate connections between the first circuits, the second circuits, and the third circuits, and filter between the tables to identify the first, the second, and the third circuits in the circuit design that have been optimized away during the synthesis.
20 . The circuit design system of claim 16 , wherein the logic synthesis and optimization tools provide third data for the user interface that indicate a root cause of one of the optimizations affecting the first circuits, the second circuits, and the third circuits.