Method and apparatus for supporting automatic testbench parallelism and serial equivalence checking during verification

1. A method for designing a system on a target device, comprising:

performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system, wherein the serial testbench comprises a function; and

performing verification on the system that examines a parallel nature of the system by using the serial testbench to test the system by issuing a subsequent call to the function before a previous call to the function has been completed.

2. The method of claim 1 , wherein the parallel nature of the system allows a plurality of calls to the function to be made in parallel to process a plurality of input vectors.

3. The method of claim 1 , wherein the serial testbench tests the system serially by issuing a subsequent call to the function after a previous call to the function has been completed.

4. The method of claim 1 , wherein the target device is a field programmable gate array.

5. The method of claim 1 , wherein performing verification on the system comprises:

generating a first instance and a second instance of the system;

executing the serial testbench to generate input vectors;

passing the input vectors to the first instance of the system to test the system; and

passing the input vectors to the second instance to test the system, wherein the first instance of the system processes the input vectors at a rate faster than which the second instance of the system processes the input vectors, and wherein one or more results generated by the first instance of the system can be used to resolve data dependencies from passing the input vectors to the second instance of the system.

6. The method of claim 5 , wherein passing the input vectors to the second instance of the system comprises issuing a subsequent call to the function before a previous call to the function has been completed.

7. The method of claim 5 further comprising:

comparing results generated from passing the input vectors to the first instance of the system with results generated from passing the input vectors to the second instance of the system; and

generating a notification in response to whether the results are equivalent.

8. The method of claim 7 , wherein equivalency is based on user definition.

9. The method of claim 5 , wherein the first instance of the system is a software version of the system that does not originate from the HDL of the system, and the second instance of the system is a hardware version of the system that originates from the HDL of the system.

10. The method of claim 9 , wherein the first instance of the system is executed on a computer system executing the serial testbench, and wherein the second instance of the system is executed on one of a simulator system and the target device.

11. The method of claim 5 , wherein the first instance of the system and the second instance of the system are hardware versions of the system that originate from the HDL of the system.

12. The method of claim 11 , wherein the first instance of the system and the second instance of the system are executed on one of a simulator system and the target device.

13. The method of claim 1 , wherein verification is performed after HDL compilation of the system where synthesis, placement, and routing is performed on the system.

14. The method of claim 1 , wherein verification is performed after the system is programmed on the target device.

15. The method of claim 1 , wherein the high level language is a serial language.

16. A method for designing a system on a target device, comprising:

performing high-level compilation on a high-level language source file to generate a hardware description language (HDL) of the system and a serial testbench for the system; and

performing verification on the system that examines a parallel nature of the system by using the serial testbench, wherein performing verification on the system comprises:

executing the serial testbench to generate input vectors;

passing the input vectors to an instance of the system a first time; and

passing the input vectors to the instance of the system a second time, wherein one or more results generated from passing the input vectors to the instance of the system the first time can be used to resolve data dependencies from passing the input vectors to the instance of the system the second time.

17. A non-transitory computer readable medium including a sequence of instructions stored thereon for causing a computer to execute a method for performing verification on a system, comprising:

executing a serial testbench, that tests the system serially by issuing a subsequent call to a function after a previous call to the function has been completed, to generate input vectors;

passing the input vectors to a first instance of the system; and

passing the input vectors to a second instance of the system, wherein one or more results generated by the first instance of the system can be used to resolve data dependencies from passing the input vectors to the second instance of the system.

18. The non-transitory computer readable medium of claim 17 , wherein passing the input vectors to the first instance of the system is performed concurrently with passing the input vectors to the second instance of the system.

19. The non-transitory computer readable medium of claim 17 , wherein passing the input vectors to the second instance of the system is performed after the first instance of the system has completed processing the input vectors.

20. The non-transitory computer readable medium of claim 19 , wherein passing the input vectors to the first instance of the system is performed after high level language compilation, and passing the input vectors to the second instance of the system is performed after hardware description language compilation.

21. The non-transitory computer readable medium of claim 19 , wherein the first instance of the system and the second instance of the system are implemented by a same component.

22. A system designer, comprising:

a high-level compilation unit that generates a hardware description language (HDL) of a system and a serial testbench for the system from a high-level language source file, wherein the serial testbench comprises a function; and

a verification unit that examines a parallel nature of the system by using the serial testbench to test the system by issuing a subsequent call to the function before a previous call to the function has been completed.

23. The system designer of claim 22 , wherein the parallel nature of the system allows a plurality of calls to the function to be made in parallel to process a plurality of input vectors.

24. The system designer of claim 22 , wherein the serial testbench tests the system serially by issuing a subsequent call to the function after a previous call to the function has been completed.

25. The system designer of claim 22 , wherein the system designer comprises:

an instance generation unit that generates a first instance and a second instance of the system;

an input vector management unit that executes the serial testbench to generate input vectors; and

an instance management unit that passes the input vectors to the first and second instances of the system to test the system, and that regulates the first instance of the system such that the first instance of the system processes the input vectors at a rate faster than which the second instance of the system processes the input vectors, and wherein one or more results generated by the first instance of the system can be used to resolve data dependencies from passing the input vectors to the second instance of the system.