Embedded network on chip accessible to programmable logic fabric of programmable logic device in multi-dimensional die systems
An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die, such that the programmable logic fabric may include a first region of programmable logic fabric and a second region of programmable logic fabric. The first region of programmable logic fabric is configured to be programmed with a circuit design that operates on a first set of data. The integrated circuit may also include network on chip (NOC) circuitry disposed on a second integrated circuit die, such that the NOC circuitry is configured to communicate data between the first integrated circuit die and the second integrated circuit die.
1. A multi-die package, comprising:
a first plurality of dies respectively comprising a processor;
a second die comprising cache memory;
a third die, wherein the third die and the second die have a stacked configuration; and
a fourth die communicatively coupling the plurality of first dies and the third die, wherein the fourth die comprises thermal monitoring circuitry, voltage control circuitry, and a plurality of memory interfaces, and wherein the fourth die is configurable to:
route data between the plurality of first dies; and
route data between off-package memory and the plurality of first dies using the plurality of memory interfaces.
2. The multi-die package of claim 1 , wherein the fourth die comprises peripheral circuitry configurable to route data between the second die and an off-package electronic device.
3. The multi-die package of claim 1 , wherein the fourth die comprises a Peripheral Component Interconnect Express (PCIe) interface.
4. The multi-die package of claim 3 , wherein the plurality of memory interfaces comprises one or more double data rate (DDR) memory interfaces.
5. The multi-die package of claim 1 , comprising a substrate onto which the fourth die is mounted, wherein the substrate routes data between the fourth die and the off-package memory.
6. The multi-die package of claim 1 , wherein the third die comprises one or more processor cores.
7. The multi-die package of claim 1 , wherein the third die is a die of the first plurality of dies.
8. The multi-die package of claim 1 , wherein the third die comprises additional voltage control circuitry and additional thermal monitoring circuitry configurable to scale a voltage based on a temperature measurement from a temperature sensor.
9. The multi-die package of claim 1 , wherein the plurality of first dies comprises four dies.
10. A multi-die package comprising:
a processor die comprises first voltage control circuitry and first thermal monitoring circuitry;
an input/output (I/O) die comprises a memory interface configurable to route data between the processor die and off-package memory; and
a cache die, wherein the cache die and the processor die have a three-dimensional stacked configuration.
11. The multi-die package of claim 10 , wherein the processor die comprises additional cache memory.
12. The multi-die package of claim 10 , wherein the I/O die is configurable to route data between the processor die and a second processor die.
13. The multi-die package of claim 10 , comprising a plurality of processor dies and a plurality of cache dies, wherein each respective cache die of the plurality of cache dies is in a stacked configuration with a respective processor die of the plurality of processor dies.
14. The multi-die package of claim 10 , wherein a size of the cache die and a size of the processor die are different.
15. The multi-die package of claim 10 , wherein the I/O die comprises second voltage control circuitry and second thermal monitoring circuitry.
16. The multi-die package of claim 10 , wherein the processor die comprises a plurality of processor cores.
17. A multi-die package comprising:
a plurality of first dies comprising a respective plurality of processor cores, wherein each first die of the plurality of first dies comprises voltage control circuitry and thermal monitoring circuitry;
a second die comprising a memory interface configurable to route data between the plurality of first dies and off-package memory; and
a plurality of third dies, wherein each die of the plurality of third dies is in a stacked configuration with a respective die of the plurality of first dies.
18. The multi-die package of claim 17 , wherein:
the second die comprises a Peripheral Component Interconnect Express (PCIe) interface; and
the memory interface comprises a double data rate (DDR) memory interface.
19. The multi-die package of claim 17 , wherein the second die is configurable to route data between the dies of the plurality of first dies.
20. The multi-die package of claim 17 , wherein respective dies of the plurality of first dies comprise memory.
21. The multi-die package of claim 17 , wherein the plurality of first dies respectively comprise additional cache memory.
22. The multi-die package of claim 17 , wherein a size of a die of the plurality of third dies is different from a size of a dies of the plurality of first dies is different.