Sharing a JTAG interface among multiple partitions
An integrated circuit device includes a first partition and a second partition. The integrated circuit device also includes a Joint Test Action Group (JTAG) system that controls at least a portion of the integrated circuit device via logic signals. The JTAG system includes a JTAG interface that receives logic signals and a first JTAG hub instantiated in the first partition communicatively coupled to the JTAG interface. The integrated circuit device further includes a second JTAG hub instantiated in the second partition communicatively coupled to the first JTAG hub via a bridge.
1. An integrated circuit device comprising:
a first partition and a second partition, wherein the first partition is reconfigurable without reconfiguring the second partition, wherein the second partition is reconfigurable without reconfiguring the first partition; and
a boundary scan system configured to control at least a portion of the integrated circuit device via a plurality of logic signals, wherein the boundary scan system comprises:
a boundary scan interface configured to receive the plurality of logic signals;
a first boundary scan hub configured in the first partition and being communicatively coupled to the boundary scan interface; and
a second boundary scan hub configured in the second partition and being communicatively coupled to the first boundary scan hub via a bridge.
2. The integrated circuit device of claim 1 , wherein the second partition comprises a system level debugging (SLD) host endpoint, wherein the second boundary scan hub is communicatively coupled to the SLD host endpoint and the SLD host endpoint is communicatively coupled to the bridge.
3. The integrated circuit device of claim 1 , wherein the second partition is nested in the first partition.
4. The integrated circuit device of claim 1 , wherein the first partition and the second partition are sibling partitions.
5. The integrated circuit device of claim 1 , wherein the boundary scan system is configured to send a set of information payload bits to the second boundary scan hub using an instruction sequence of bits, wherein the instruction sequence comprises:
a first set of select bits that identify the bridge;
a second set of select bits that identify the second boundary scan hub; and
the set of information payload bits.
6. The integrated circuit device of claim 1 , comprising a first system level debugging (SLD) agent endpoint coupled to the first boundary scan hub in the first partition, and a second SLD agent endpoint coupled to the second boundary scan hub in the second partition.
7. The integrated circuit device of claim 6 , wherein the boundary scan system is configured to send a set of information payload bits to the second SLD agent endpoint using an instruction sequence of bits, wherein the instruction sequence comprises:
a first set of select bits that identify the bridge;
a second set of select bits that identify the second SLD agent endpoint; and
the set of information payload bits.
8. The integrated circuit device of claim 6 , wherein the first SLD agent endpoint and the second SLD agent endpoint each comprises an In-System Sources and Probes (ISSP) interface, a SignalTap (STAP) interface, an In-System Memory Content Editor (ISMCE) interface, a boundary scan Debug Bus Master interface, a boundary scan Debug Packet Streamer interface, or a Microprocessor Debugger Module interface.
9. The integrated circuit device of claim 1 , wherein the integrated circuit device comprises a field programmable gate array (FPGA).
10. A boundary scan system comprising:
a boundary scan interface of an integrated circuit configured to receive a plurality of boundary scan logic signals;
a first boundary scan hub configured in a first partition of the integrated circuit and communicatively coupled to the boundary scan interface; and
a second boundary scan hub configured in a second partition of the integrated circuit and communicatively coupled to the first boundary scan hub via a bridge, wherein the first partition is reconfigurable without reconfiguring the second partition, wherein the second partition is reconfigurable without reconfiguring the first partition.
11. The boundary scan system claim 10 , comprising a third boundary scan hub configured in a third partition of the integrated circuit and communicatively coupled to the second boundary scan hub via a second bridge.
12. The boundary scan system claim 11 , wherein the third partition is nested in the second partition and the second bridge is configured in the second partition.
13. The boundary scan system claim 11 , wherein the second partition and the third partition are sibling partitions and the second bridge is configured in the second partition.
14. A method comprising:
creating a first partition in an integrated circuit;
creating a second partition in the integrated circuit, wherein the first partition is reconfigurable without reconfiguring the second partition, wherein the second partition is reconfigurable without reconfiguring the first partition;
configuring a first boundary scan hub in the first partition, the first boundary scan hub being communicatively coupled to a boundary scan interface;
configuring a second boundary scan hub in the second partition; and
configuring a bridge to communicatively couple the first boundary scan hub to the second boundary scan hub.
15. The method of claim 14 , wherein the bridge is configured in the first partition.
16. The method of claim 14 , comprising configuring a system level debugging (SLD) host endpoint in the second partition, the SLD host endpoint communicatively coupling the second boundary scan hub to the bridge.
17. The method of claim 14 , comprising sending a set of information payload bits to the second boundary scan hub using an instruction sequence of bits, wherein the instruction sequence comprises:
a first set of select bits that identify the bridge;
a second set of select bits that identify the second boundary scan hub; and
the set of information payload bits.
18. The method of claim 17 , wherein the first boundary scan hub comprises a first set of data registers and a first instruction register that shifts in the instruction sequence, the second boundary scan hub comprises a second set of data registers and a second instruction register that shifts in at least a portion of the instruction sequence, and a total number of shifts to shift the instruction sequence into the first instruction register and shift the instruction sequence into the second instruction register matches a total number of data registers in the first set of data registers and the second set of data registers.
19. The method of claim 14 , wherein comprising configuring an SLD agent endpoint in the second partition communicatively coupled to the second boundary scan hub.
20. The method of claim 19 , comprising sending a set of information payload bits to the SLD agent endpoint using an instruction sequence of bits, wherein the instruction sequence comprises:
a first set of select bits that identify the bridge;
a second set of select bits that identify the SLD agent endpoint; and
the set of information payload bits.