Stacked programmable integrated circuitry with smart memory
Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.
1. An active interposer comprising:
a programmable coarse-grain routing network having channels forming a deterministic routing path; and
an array of memory blocks accessible using the programmable coarse-grain routing network, wherein at least one memory block in the array of memory blocks is operable in a state-machine-driven mode to perform a sequence of operations, and wherein the at least one memory block is operable in a microcontroller mode to perform multicycle operations with a higher cycle count than the operations performed during the state-machine-driven mode.
2. The active interposer of claim 1 , wherein the sequence of operations comprises operations selected from the group consisting of: a data update, a data comparison, and a linked list traversal.
3. The active interposer of claim 1 , wherein the at least one memory block is operable as content addressable memory (CAM) in the state-machine-driven mode.
4. The active interposer of claim 1 , wherein the at least one memory block is operable as cache memory in the state-machine-driven mode.
5. The active interposer of claim 1 , wherein the at least one memory block is further operable in a simple memory access mode to perform operations selected from the group consisting of: a direct memory access and a streaming memory access.
6. The active interposer of claim 1 , wherein the multicycle operations comprise operations selected from the group consisting of: data arrangement operations, direct memory access controller operations, linked list traversal operations, programmable logic control operations, and memory expansion operations.
7. The active interposer of claim 1 , wherein the array of memory blocks are composable into different sizes.
8. The active interposer of claim 1 , wherein the at least one memory block is further operable in an idle mode.
9. An active interposer, comprising:
a programmable coarse-grain routing network having channels forming a deterministic routing path operable to communicatively couple to programmable logic disposed in a different spatial plane relative to the programmable coarse-grain routing network;
an array of memory blocks accessible using the programmable coarse-grain routing network; and
at least one functional block that is formed within the array of memory blocks, that is accessible using the programmable coarse-grain routing network, and that is configured to perform a different function than the array of memory blocks.
10. The active interposer of claim 9 , wherein the at least one function block comprises a hardened block selected from the group consisting of: a protocol bridge and global routing control block, a global routing buffer block, a direct memory access block, and a microcontroller.
11. The active interposer of claim 9 , wherein the at least one functional block is implemented using a memory block.
12. The active interposer of claim 9 , wherein the programmable coarse-grain routing network comprises an array of configurable 4-port switch box circuits.
13. The active interposer of claim 12 , wherein the programmable coarse-grain routing network further comprises configurable 3-port connection box circuits that are used to directly access the array of memory blocks and the at least one functional block.
14. An active interposer comprising:
a memory block that comprises:
a state machine that is active during a first mode to perform operations having a first cycle count; and
a program counter that is active during a second mode to perform operations having a second cycle counter that is higher than the first cycle count.
15. The active interposer of claim 14 , wherein the memory block further comprises a power management circuit configured to manage a power state of the memory block.
16. The active interposer of claim 14 , wherein the memory block further comprises a counter configured to support programmable burst lengths.
17. The active interposer of claim 14 , wherein the memory block further comprises a start of packet (SOP) input port and a start of packet (SOP) output port.
18. The active interposer of claim 14 , wherein the memory block further comprises:
a data input port; and
a valid input port configured to receive a valid signal indicating whether signals at the data input port are valid.
19. The active interposer of claim 14 , wherein the memory block is further operable to perform error-correcting code (ECC) operations.
20. The active interposer of claim 14 , comprising a programmable coarse-grain routing network having channels forming a deterministic routing path operable to communicatively couple between the memory block and programmable logic disposed in a different spatial plane relative to the memory block.