Strict-sense minimal spanning switch non-blocking architecture
View Patent ↗The present invention discloses an apparatus to implement a m=n Non-Blocking Minimal Spanning Switch, where n=the total number of data input signals and m=the total number of data output signals and m=the number of crossbar connections in each switch. Data is input to the switch as a plurality of frames, whereby each crossbar connection contains a framer which detects framing patterns in the data. Skewed data is re-aligned and buffered so that the data output by each crossbar connection is equal and identical, thus any crossbar connection may be used to ensure a connection, eliminating the possibility of data interrupts.
1. Switching circuitry comprising:
a plurality of cross-bar circuitries each of which is configured to receive a same plurality of data input signals, wherein
each cross-bar circuitry of the plurality of cross-bar circuitries comprises:
a plurality of alignment circuitries, wherein each alignment circuitry of the plurality of alignment circuitries is configured to:
determine a start of frame signal associated with the received plurality of data input signals, and
align each respective data input signal of the received plurality of data input signals based on the determined start of frame signal; and
selection circuitry configured to select between signals output by the plurality of alignment circuitries.
2. The switching circuitry of claim 1 , wherein framer circuitry is configured to determine the start of frame signal of the each respective data input signal.
3. The switching circuitry of claim 2 , wherein:
a data input signal of the plurality of data input signals comprises a plurality of data frames and framer circuitry,
the each alignment circuitry of the plurality of alignment circuitries further comprises buffer circuitry, and
the framer circuitry is further configured to write a data frame of the plurality of data frames into data locations within the buffer circuitry, wherein the data locations are determined based on the determined start of frame signal.
4. The switching circuitry of claim 1 , wherein
a data input signal of the plurality of data input signals comprises a plurality of data frames, and
the determined start of frame signal indicates a starting bit of a data frame of the plurality of data frames.
5. The switching circuitry of claim 1 , wherein the each alignment circuitry of the plurality of alignment circuitries further comprises a First-In-First-Out (FIFO) buffer circuitry.
6. The switching circuitry of claim 1 , wherein:
each data input signal received by the each alignment circuitry of the plurality of alignment circuitries comprises a plurality of component signals,
the each alignment circuitry is further configured to align and separately output each component signal of the plurality of component signals, and
the selection circuitry is further configured to select, for output by the each cross-bar circuitry, an aligned component signal of the plurality of aligned component signals separately output by the each alignment circuitry.
7. The switching circuitry of claim 1 , wherein a number of data input signals in the plurality of data input signals is equal to a number of cross-bar circuitries.
8. The switching circuitry of claim 1 , wherein the switching circuitry is a non-blocking minimal spanning switch circuitry.
9. A method comprising:
receiving, with each cross-bar circuitry of a plurality of cross-bar circuitries, a same plurality of data input signals,
determining, with a plurality of alignment circuitries of the each cross-bar circuitry, a start of frame signal associated with the received plurality of data input signals,
aligning, with the plurality of alignment circuitries, each respective data input signal of the received plurality of data input signals based on the determined start of frame signal, and
selecting, with selection circuitry, between signals output by the plurality of alignment circuitries using selection circuitry.
10. The method of claim 9 , wherein the start of frame signal of the each respective data input signal is determined by framer circuitry.
11. The method of claim 10 , wherein:
a data input signal comprises a plurality of data frames and framer circuitry,
the each alignment circuitry further comprises buffer circuitry, and
the framer circuitry is further configured to write a data frame of the plurality of data frames into data locations within the buffer circuitry, wherein the data locations are determined based on the determined start of frame signal.
12. The method of claim 9 , wherein:
a data input signal in the plurality of data input signals comprises a plurality of data frames, and
the determined start of frame signal indicates a starting bit of a data frame of the plurality of data frames.
13. The method of claim 9 , wherein the each alignment circuitry further comprises a First-In-First-Out (FIFO) buffer circuitry.
14. The method of claim 9 , wherein:
each data input signal comprises a plurality of component signals,
the each alignment circuitry is further configured to align and separately output each component signal of the plurality of component signals, and
the selection circuitry of the each cross-bar circuitry is further configured to select, for output by the each cross-bar circuitry, an aligned component signal of the plurality of separately output aligned component signals.
15. The method of claim 9 , wherein a number of data input signals in the plurality of data input signals is equal to a number of the cross-bar circuitries.
16. The method of claim 9 , wherein the plurality of cross-bar circuitries are part of a non-blocking minimal spanning switch circuitry.
17. Switching circuitry comprising:
a plurality of cross-bar circuitries, wherein each cross-bar circuitry of the plurality of cross-bar circuitries comprises:
a plurality of framer circuitries, wherein each framer circuitry of the plurality of framer circuitries is configured to:
determine a start of frame signal of a respective data input signal of a same plurality of received data input signals; and
write the respective data input signal into data locations within a respective buffer circuitry of a plurality of buffer circuitries, wherein the data locations are determined based on the determined start of frame signal.
18. The switching circuitry of claim 17 , wherein a number of data input signals in the plurality of data input signals is equal to a number of the cross-bar circuitries.