Granted Patent B2

US 12,452,223 · App. 17/559,875 · Granted Oct 21, 2025

Inventors: Choon Yip Soo (Bayan Lepas, MY); Su Wei Lim (Bayan Lepas, MY); Si Xing Saw (Bukit Mertajam, MY); Markos Papadonikolakis (London, GB)

Assignee: Altera Corporation

H04L63/068H04L63/0428H04L63/108

Abstract

Claims (55)

1. An integrated circuit device, comprising:

a counter, wherein the counter provides an elapsed time to scheduler circuitry;

encryption circuitry to encrypt a data packet, wherein the encryption circuitry indicates an initial elapsed time upon receipt of the data packet; and

the scheduler circuitry to receive the encrypted data packet from the encryption circuitry, wherein the scheduler circuitry:

monitors a duration of time associated with egress of the encrypted data packet, wherein the scheduler circuitry determines the duration of time associated with egress of the encrypted data packet based on a difference between the initial elapsed time indicated by the encryption circuitry and the elapsed time provided by the counter;

holds the encrypted data packet until the duration of time matches a threshold duration of time; and

transmits the encrypted data packet in response to the duration of time matching the threshold duration of time.

2. The integrated circuit device of claim 1 , wherein the duration of time comprises a duration of time elapsed since receipt of the data packet by the encryption circuitry.

3. The integrated circuit device of claim 1 , comprising:

ingress circuitry configured to receive a previously encrypted data packet;

decryption circuitry to decrypt the previously encrypted data packet to form the data packet prior to encryption of the data packet via the encryption circuitry, wherein the duration of time comprises a duration of time elapsed since receipt of the data packet by the decryption circuitry.

4. The integrated circuit device of claim 3 , comprising correction field update circuitry to:

receive the decrypted data packet decrypted by the decryption circuitry;

update a correction field of the decrypted data packet; and

transmit the decrypted data packet to the encryption circuitry after updating the correction field of the decrypted data packet.

5. The integrated circuit device of claim 1 , comprising processing cores, wherein the scheduler circuitry transmits the encrypted data packet to the processing cores in response to the duration of time matching the threshold duration of time.

6. The integrated circuit device of claim 5 , wherein the processing cores transmit the encrypted data packet from the integrated circuit device to a target recipient device.

7. The integrated circuit device of claim 1 , wherein the encryption circuitry comprises media access control security encryption circuitry.

8. An integrated circuit device, comprising:

encryption circuitry configurable to:

encrypt data via an encryption process, wherein the encryption process occurs during a first duration of time; and

update metadata associated with the encrypted data to indicate a first time in which the data is received by the encryption circuitry; and

scheduler circuitry configurable to receive the encrypted data from the encryption circuitry, wherein the scheduler circuitry is configurable to:

hold the encrypted data for a second duration of time; and

determine a total duration of time since receipt of the data at the encryption circuitry based on a difference between the first time in which the encryption circuitry receives the data and a second time received from a counter while holding the encrypted data;

transmit the encrypted data in response to the second duration of time indicating that the total duration of time since receipt of the data at the encryption circuitry matches a threshold duration of time, wherein the total duration of time comprises a sum of the first duration of time and the second duration of time.

9. The integrated circuit device of claim 8 , wherein the encryption circuitry comprises media access control security encryption circuitry.

10. The integrated circuit device of claim 8 , comprising precision time protocol circuitry configurable to transmit the data to the encryption circuitry, wherein the precision time protocol circuitry is configurable to transmit a timestamp based on the threshold duration of time, and the timestamp is indicative of a time of transmission of the encrypted data via the integrated circuit device.

11. The integrated circuit device of claim 10 , comprising processing cores configurable to:

receive the encrypted data transmitted by the scheduler circuitry;

transmit a follow-up message to the precision time protocol circuitry upon receipt of the encrypted data from the scheduler circuitry; and

transmit the encrypted data from the integrated circuit device to a target recipient device.

12. The integrated circuit device of claim 11 , wherein the precision time protocol circuitry is configurable to transmit the timestamp to the processing cores based on the follow-up message.

13. An integrated circuit device, comprising:

precision time protocol circuitry configured to transmit a packet and corresponding metadata;

encryption circuitry configured to:

receive the packet and the corresponding metadata from the precision time protocol circuitry;

update the corresponding metadata to indicate a time of receipt of the packet at the encryption circuitry from the precision time protocol circuitry; and

encrypt the packet; and

scheduler circuitry configured to:

receive the encrypted packet and updated corresponding metadata from the encryption circuitry;

hold the encrypted packet and the updated corresponding metadata for a duration of time based on the time of receipt of the encrypted packet at the encryption circuitry indicated by the updated corresponding metadata; and

transmit the encrypted packet in response to determining that the duration of time indicates that a total duration of time since receipt of the packet at the encryption circuitry matches a threshold duration of time, wherein the total duration of time comprises the duration of time in which the scheduler circuitry holds the encrypted packet and the updated corresponding metadata and an additional duration of time in which the encryption circuitry encrypts the packet.

14. The integrated circuit device of claim 13 , wherein the precision time protocol circuitry is configured to transmit an additional packet and corresponding additional metadata in parallel with the packet and the corresponding metadata, and the encryption circuitry is configured to encrypt the additional packet and comprises:

a multiplexer configured to select between the packet with the corresponding metadata and the additional packet with the corresponding additional metadata for encryption in the encryption circuitry; and

a demultiplexer configured to route the encrypted packet with the corresponding metadata down a first path and to route the encrypted additional packet with the corresponding additional metadata down a second path.

15. The integrated circuit device of claim 14 , wherein the scheduler circuitry is configured to:

monitor a first duration of time elapsed since receipt of the packet at the encryption circuitry and a second duration of time elapsed since receipt of the additional packet at the encryption circuitry;

transmit the encrypted packet in response to determining that the first duration of time matches a first threshold duration of time; and

transmit the encrypted additional packet in response to determining that the second duration of time matches a second threshold duration of time.

16. The integrated circuit device of claim 13 , wherein the precision time protocol circuitry is configured to transmit the packet and the corresponding metadata during performance of precision time protocol, and the precision time protocol comprises a one-step operation mode or a two-step operation mode.

17. The integrated circuit device of claim 13 , comprising a counter, wherein the counter provides an elapsed time to the scheduler circuitry, and the scheduler circuitry determines the total duration of time since receipt of the packet at the encryption circuitry based on the elapsed time provided by the counter.

18. The integrated circuit device of claim 17 , wherein the scheduler circuitry determines the total duration of time since receipt of the packet at the encryption circuitry based on a difference between the initial elapsed time indicated by the encryption circuitry and the time of receipt of the encrypted packet at the encryption circuitry indicated by the updated corresponding metadata.

19. The integrated circuit device of claim 13 , wherein the additional duration of time is variable.

20. The integrated circuit device of claim 19 , wherein the duration of time and the additional duration of time are inversely proportional to one another.

Assignments (3)

Continuity (1)

References Cited (12)