High-speed core interconnect for multi-die programmable logic devices
Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
1. A programmable logic device comprising:
a first die;
a second die;
a third die coupled to the first die via a first interconnect bridge and coupled to the second die via a second interconnect bridge, wherein the first interconnect bridge and the second interconnect bridge are used for one or more data transfers between the first die and the second die, wherein the one or more data transfers are assigned to direct routing in response to the one or more data transfers traversing the third die, wherein the third die is coupled to a plurality of interconnect layers, and wherein the plurality of interconnect layers comprises one or more hardened data buses used to create one or more routes between different regions of a programmable fabric layer of the third die.
2. The programmable logic device of claim 1 , wherein the programmable fabric layer of the third die comprises programmable logic.
3. The programmable logic device of claim 1 , wherein the third die comprises an input/output (I/O) die that comprises transceiver circuitry.
4. The programmable logic device of claim 1 , wherein at least one interconnect layer of the plurality of interconnect layers comprises a core interconnect.
5. The programmable logic device of claim 4 , wherein the core interconnect comprises a plurality of repeaters.
6. The programmable logic device of claim 4 , wherein the core interconnect is configured to couple a first interface to a second interface.
7. The programmable logic device of claim 6 , wherein the first interface is configured to couple the first die to the third die, and wherein the second interface is configured to couple the second die to the third die.
8. The programmable logic device of claim 6 , wherein the first interface comprises a microbump interface.
9. The programmable logic device of claim 1 , wherein the first die comprises programmable logic.
10. The programmable logic device of claim 1 , wherein the second die comprises programmable logic.
11. A data processing system, comprising:
a programmable logic device, comprising:
a first die coupled to a programmable die via a first interface; and
a second die coupled to the programmable die via a second interface, wherein
the programmable die comprises a core interconnect that couples to routing circuitry, and wherein the routing circuitry is configured to dynamically reconfigure one or more routes in a programmable fabric layer of the programmable die; and
a host processor configured to assign a first data transfer between the first die and the second die as regular routing in response to determining that the first data transfer does not traverse the programmable die.
12. The data processing system of claim 11 , wherein the core interconnect comprises a set of data channels.
13. The data processing system of claim 12 , wherein the host processor is configured to assign priority to one or more data transfers in response to a number of the one or more data transfers exceeding available number of the data channels in the core interconnect.
14. The data processing system of claim 11 , wherein the host processor is configured to:
determine a second data transfer between the first die and the second die;
determine a second priority for assignment of the second data transfer based on a timing specification of a circuit design of the programmable logic device;
compare a first priority of the first data transfer and the second priority; and
assign a portion of programmable logic of the programmable die to the second data transfer.
15. The data processing system of claim 11 , wherein the first interface is configured to couple to the first die through an interconnect bridge.
16. The data processing system of claim 11 , wherein the core interconnect is configured to couple the first interface to the second interface.
17. The data processing system of claim 11 , wherein the programmable logic device comprises a second programmable die coupled to the second die, and wherein the second die comprises a second core interconnect that couples the programmable die to the second programmable die.
18. A method comprising:
determining a first data transfer between a first region of a programmable logic device and a second region of the programmable logic device, wherein the first region is disposed in a first die of the programmable logic device, wherein the second region is disposed in a second die of the programmable logic device, wherein the first die is coupled to a third die via a first interface, wherein the second die is coupled to the third die via a second interface, and wherein the third die is coupled to a plurality of interconnect layers comprising one or more hardened data buses used to create one or more routes between different regions of a programmable fabric layer of the third die;
assigning the first data transfer to direct routing in response to determining that the first data transfer traverses the third die of the programmable logic device;
determining a second data transfer between a third region and a fourth region, wherein the third region is disposed in the first die, and wherein the fourth region is disposed in the second die; and
assigning the second data transfer to regular routing in response to determining that the second data transfer does not traverse the third die of the programmable logic device.
19. The method of claim 18 , wherein at least one interconnect layer of the plurality of interconnect layers comprises a core interconnect.
20. The method of claim 18 , wherein the third die comprises an input/output (I/O) die that comprises transceiver circuitry.