IP Library Granted Patent US 12,425,030
Granted Patent B2
US 12,425,030 · App. 17/555,253 · Granted Sep 23, 2025

Systems and methods for configurable interface circuits

Inventors: Paul Rotker (Stow, MA); Lai Guan Tang (Bayan Lepas, MY); Luis Hau (Fremont, CA); Ilya Ganusov (San Jose, CA)
Assignee: Altera Corporation
H03K19/017581
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Quick Facts
Patent No.
US 12,425,030
App. No.
17/555,253
Granted
Sep 23, 2025
Kind
B2
Abstract

An integrated circuit includes a region of logic circuits, first and second selector circuits, a first interface circuit for exchanging information with a first type of device according to a first communication protocol, and a second interface circuit for exchanging information with a second type of device according to a second communication protocol. The first selector circuit is configurable to provide signals between the region of the logic circuits and a selected one of the first or second interface circuits. The second selector circuit is configurable to provide signals between the selected one of the first or second interface circuits and the first or second type of device.

Claims (44)

1. An integrated circuit comprising:

a region of logic circuits;

first and second selector circuits;

a first interface circuit for exchanging information with a first device according to a first communication protocol; and

a second interface circuit for exchanging information with a second device according to a second communication protocol, wherein the first selector circuit is configurable to provide signals between the region of the logic circuits and a selected one of the first or the second interface circuits, wherein the second selector circuit is configurable to provide signals between the selected one of the first or the second interface circuits and the first or the second device,

wherein the first selector circuit is coupled to at least one of the logic circuits and to the first and the second interface circuits, and wherein the second selector circuit is coupled to the first and the second interface circuits and to an external terminal of the integrated circuit.

2. The integrated circuit of claim 1 further comprising:

third and fourth selector circuits;

a third interface circuit for exchanging information with the first device according to the first communication protocol; and

a fourth interface circuit for exchanging information with the second device according to the second communication protocol, wherein the third selector circuit is configurable to provide signals between the region of the logic circuits and a selected one of the third or the fourth interface circuits, and wherein the fourth selector circuit is configurable to provide signals between the selected one of the third or the fourth interface circuits and the first or the second device.

3. The integrated circuit of claim 2 further comprising:

fifth and sixth selector circuits;

a fifth interface circuit for exchanging information with the first device according to the first communication protocol; and

a sixth interface circuit for exchanging information with the second device according to the second communication protocol, wherein the fifth selector circuit is configurable to provide signals between the region of the logic circuits and a selected one of the fifth or the sixth interface circuits, and wherein the sixth selector circuit is configurable to provide signals between the selected one of the fifth or the sixth interface circuits and the first or the second device.

4. The integrated circuit of claim 1 further comprising:

input-output circuits configurable to exchange signals between the region of the logic circuits and an external electronic system.

5. The integrated circuit of claim 1 , wherein each of the first selector circuit and the second selector circuit is configurable to function as a multiplexer circuit or as a demultiplexer circuit.

6. The integrated circuit of claim 1 , wherein the first device is a processing integrated circuit, and wherein the second device is one of a transceiver integrated circuit or a memory integrated circuit.

7. The integrated circuit of claim 1 , wherein the first selector circuit is configurable to provide bidirectional communications between at least one of the logic circuits and the selected one of the first or the second interface circuits, and wherein the second selector circuit is configurable to provide bidirectional communications between the selected one of the first or the second interface circuits and an additional integrated circuit.

8. The integrated circuit of claim 1 , wherein the integrated circuit is a programmable logic integrated circuit, and wherein the region of the logic circuits comprises programmable logic circuits.

9. An integrated circuit package comprising:

a first integrated circuit comprising first and second selector circuits, a first interface circuit for exchanging information according to a first communication protocol, and a second interface circuit for exchanging information according to a second communication protocol; and

a second integrated circuit coupled to the first integrated circuit, wherein the first and the second selector circuits are configurable to select one of the first interface circuit or the second interface circuit to exchange information with the second integrated circuit through first conductors in the integrated circuit package.

10. The integrated circuit package of claim 9 further comprising:

a third integrated circuit coupled to the first integrated circuit, wherein the first integrated circuit further comprises a third interface circuit for exchanging information according to the first communication protocol, a fourth interface circuit for exchanging information according to the second communication protocol, and third and fourth selector circuits that are configurable to select one of the third interface circuit or the fourth interface circuit to exchange information with the third integrated circuit through second conductors in the integrated circuit package.

11. The integrated circuit package of claim 10 further comprising:

a fourth integrated circuit coupled to the first integrated circuit, wherein the first integrated circuit further comprises a fifth interface circuit for exchanging information according to the first communication protocol, a sixth interface circuit for exchanging information according to the second communication protocol, and fifth and sixth selector circuits that are configurable to select one of the fifth interface circuit or the sixth interface circuit to exchange information with the fourth integrated circuit through third conductors in the integrated circuit package.

12. The integrated circuit package of claim 9 , wherein the first integrated circuit is a processing integrated circuit, and wherein the second integrated circuit is one of a transceiver integrated circuit or a memory integrated circuit.

13. The integrated circuit package of claim 9 , wherein the first and the second integrated circuits are programmable logic integrated circuits.

14. The integrated circuit package of claim 9 , wherein the first integrated circuit is a programmable logic integrated circuit comprising programmable logic circuits, and wherein the first selector circuit is coupled to exchange the information between the programmable logic circuits and the selected one of the first interface circuit or the second interface circuit.

15. The integrated circuit package of claim 9 , wherein the first selector circuit is coupled to at least one logic circuit in the first integrated circuit and to the first and the second interface circuits, and wherein the second selector circuit is coupled to the first and the second interface circuits and to the second integrated circuit.

16. The integrated circuit package of claim 9 , wherein the second integrated circuit comprises a third interface circuit for exchanging information according to the first communication protocol, a fourth interface circuit for exchanging information according to the second communication protocol, and third and fourth selector circuits that are configurable to select one of the third interface circuit or the fourth interface circuit to exchange information with the selected one of the first interface circuit or the second interface circuit through the first conductors in the integrated circuit package.

17. A method for interfacing between first and second devices in an electronic system, the method comprising:

providing a first interface circuit in an integrated circuit for exchanging information with the first device according to a first data transmission protocol;

providing a second interface circuit in the integrated circuit for exchanging information with the second device according to a second data transmission protocol;

configuring a first selector circuit in the integrated circuit to provide bidirectional communications between a region of logic circuits in the integrated circuit and a selected one of the first or the second interface circuits; and

configuring a second selector circuit in the integrated circuit to provide bidirectional communications between the selected one of the first or the second interface circuits and the first or the second device.

18. The method of claim 17 further comprising:

providing a third interface circuit in the integrated circuit for exchanging information with the first device according to the first data transmission protocol;

providing a fourth interface circuit in the integrated circuit for exchanging information with the second device according to the second data transmission protocol;

configuring a third selector circuit in the integrated circuit to provide information between the region of the logic circuits and a selected one of the third or the fourth interface circuits; and

configuring a fourth selector circuit in the integrated circuit to provide information between the selected one of the third or the fourth interface circuits and the first or the second device.

19. The method of claim 17 , wherein the first device is a processing integrated circuit, and wherein the second device is one of a transceiver integrated circuit or a memory integrated circuit.

20. The method of claim 17 , wherein the integrated circuit is a processing integrated circuit.

Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2021
From: ROTKER, PAUL; TANG, LAI GUAN; HAU, LUIS; GANUSOV, ILYA
To: INTEL CORPORATION
Reel/Frame 058424/0414 →