Interface for parallel configuration of programmable devices
An integrated circuit device may include programmable logic fabric disposed on a first integrated circuit die and having configuration memory. The integrated circuit device may also include a base die that may provide memory and/or operating supporting circuitry. The first die and the second die may be coupled using a high-speed parallel interface. The interface may employ microbumps. The first die and the second die may also include controllers for the interface.
1. An integrated circuit device, comprising:
a first die comprising a memory or a register and a first controller, wherein the register comprises a plurality of memory controllers, and wherein the first controller is configured to control the plurality of memory controllers; and
a second die comprising a second controller, wherein the second controller is coupled to the first controller via a microbump interface, wherein the microbump interface comprises a plurality of channels, wherein the plurality of channels is configured to transport data or control signals from the second die to the first die or from the first die to the second die; and wherein the second die comprises network on chip circuitry, and wherein the second die is configured to receive the data or control signals transported by the microbump interface via the network on chip circuitry.
2. The integrated circuit device of claim 1 , wherein the network on chip circuitry of the second die is configured to provide an interface for the first die to send or receive the data or the control signals from systems external to the first die and the second die.
3. The integrated circuit device of claim 1 , wherein the register comprises a data register.
4. The integrated circuit device of claim 3 , wherein the data register is configured to load data employing pipelining in the first die.
5. The integrated circuit device of claim 1 , wherein the memory comprises an embedded random-access memory (ERAM) or a cache.
6. The integrated circuit device of claim 1 , wherein the network on chip (NOC) circuitry is configured to provide communication via routers between at least two sectors of a plurality of sectors in the second die.
7. The integrated circuit device of claim 1 , wherein the first die comprises programmable logic.
8. The integrated circuit device of claim 7 , wherein the memory comprises configuration memory that controls the programmable logic.
9. The integrated circuit device of claim 8 , wherein the configuration memory comprises a plurality of memory segments.
10. The integrated circuit device of claim 1 , wherein the second die comprises a second memory that is configured to store the data.
11. A method to program a programmable logic device, comprising:
sending a write request from a first controller of a first die to a second controller of a second die, wherein the first die and the second die are coupled via a plurality of channels of a microbump interface, wherein the second die comprises network on chip circuitry, wherein the first die comprises a data register and configuration memory, wherein the data register loads data employing pipeline in the first die;
transmitting configuration data or control signals from the second die to the first die using the plurality of channels of the microbump interface; and
sending the configuration data or the control signals from the first die and the second die to a device external to the first die and the second die via the network on chip circuitry.
12. The method of claim 11 , wherein the first die comprises programmable logic.
13. The method of claim 11 , comprising receiving, in the second die, a portion of the configuration data via the network on chip circuitry.
14. The method of claim 11 , comprising storing the configuration data in a memory in the second die.
15. The method of claim 11 , wherein the first die comprises groups of logic elements.
16. An electronic device, comprising:
a first die, comprising a first controller;
a second die, comprising a second controller and testing circuitry, wherein the first controller and the second controller are configured to perform a diagnostic test in the first die; and
a microbump interface configured to couple the first die to the second die; wherein the microbump interface comprises a plurality of channels, wherein the first controller and the second controller are configured to control exchange of data or control signals between the first die and the second die via the plurality of channels of the microbump interface; wherein the second die comprises network on chip circuitry, and wherein the second die is configured to receive the data or the control signals transported by the microbump interface via the network on chip circuitry.
17. The electronic device of claim 16 , wherein the first die comprises programmable fabric and configuration memory.
18. The electronic device of claim 16 , wherein the electronic device comprises a third die coupled to the second die via a second microbump interface, wherein the third die comprises a third controller, and wherein the second die comprises a fourth controller configured to couple the third controller via the second microbump interface.
19. The integrated circuit device of claim 1 , wherein the second die comprises testing circuitry, and wherein the first controller and the second controller are configured to perform a diagnostic test in the first die.
20. The electronic device of claim 16 , wherein the first die comprises a data register configured to load data employing pipeline in the first die.