Semiconductor device including gate drivers around a periphery thereof
View Patent ↗A semiconductor device and method of forming the same including, in one embodiment, a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (“LDMOS”) cells, and a metallic layer electrically coupled to the plurality of LDMOS cells. The semiconductor device also includes a plurality of gate drivers positioned along a periphery of the semiconductor die and electrically coupled to gates of the plurality of LDMOS cells through the metallic layer.
1. A semiconductor device, comprising:
a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells forming an LDMOS device;
a metallic layer electrically coupled to said plurality of LDMOS cells; and
a plurality of gate drivers positioned along a periphery on said semiconductor die and electrically coupled to gates of said plurality of LDMOS cells through said metallic layer.
2. The semiconductor device as recited in claim 1 , wherein said metallic layer is coupled to a redistribution layer.
3. The semiconductor device as recited in claim 2 , wherein said metallic layer comprises aluminum and said redistribution layer comprises copper.
4. The semiconductor device as recited in claim 1 , wherein at least one of said plurality of gate drivers comprise driver switches formed as metal oxide semiconductor (“MOS”) devices.
5. The semiconductor device as recited in claim 1 , wherein said metallic layer is configured to couple at least one of said plurality of gate drivers to a gate-drive bias voltage.
6. The semiconductor device as recited in claim 1 , wherein said metallic layer is configured to couple a control signal and a monitoring signal to said plurality of gate drivers.
7. The semiconductor device as recited in claim 1 , further comprising:
a plurality of metallic pillars distributed over and electrically coupled to a redistribution layer above said metallic layer; and
a conductive, patterned leadframe electrically coupled to said plurality of metallic pillars.
8. The semiconductor device as recited in claim 7 , wherein said semiconductor device is potted with an encapulant.
9. The semiconductor device as recited in claim 8 , wherein portions of said conductive patterned leadframe are exposed to serve as external contacts for said semiconductor device.
10. The semiconductor device as recited in claim 9 , wherein at least one of said external contacts is configured to be coupled to a printed circuit board.
11. The semiconductor device as recited in claim 10 , wherein ones of said external contacts are configured to be coupled to a plurality of decoupling devices on said printed circuit board.
12. The semiconductor device as recited in claim 10 , wherein ones of said external contacts are configured to be coupled to a plurality of decoupling devices through vias on an opposing surface of said printed circuit board.
13. The semiconductor device as recited in claim 9 , wherein at least one of said external contacts is coupled to said plurality of gate drivers.
14. The semiconductor device as recited in claim 9 , wherein at least one of said external contacts is coupled to source regions or drain regions of said plurality of said LDMOS cells through said metallic layer and said redistribution layer.
15. The semiconductor device as recited in claim 1 , wherein said metallic layer is formed as a plurality of metallic layers.
16. The semiconductor device as recited in claim 1 , further comprising a plurality of alternating source and drain metallic strips formed in said metallic layer above a substrate of said semiconductor die and parallel to and forming an electrical contact with respective ones of a plurality of source and drain regions of said LDMOS device.
17. A method of forming a semiconductor device, comprising:
forming a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells of an LDMOS device in a semiconductor die;
coupling a metallic layer to said plurality of LDMOS cells;
positioning a plurality of gate drivers along a periphery of said semiconductor die; and
coupling gates of said plurality of LDMOS cells through said metallic layer to said plurality of gate drivers.
18. The method as recited in claim 17 , further comprising:
coupling said metallic layer to a redistribution layer;
distributing over and coupling a plurality of metallic pillars to said redistribution layer;
coupling a conductive patterned leadframe to said redistribution layer by said plurality of metallic pillars; and
potting said semiconductor device with an encapulant, wherein portions of said conductive patterned leadframe are exposed to serve as external contacts for said semiconductor device.
19. The method as recited in claim 18 , wherein ones of said external contacts are coupled to a plurality of gate drivers coupled to said redistribution layer and to gates of said plurality of LDMOS cells, and ones of said external contacts are coupled to drains or sources of said plurality of LDMOS cells through said redistribution layer.
20. The method as recited in claim 17 , further comprising forming a plurality of alternating source and drain metallic strips in said metallic layer above a substrate of said semiconductor die and parallel to and forming an electrical contact with respective ones of a plurality of source and drain regions of said LDMOS device.