Techniques For Sharing Memory Interface Circuits Between Integrated Circuit Dies
A circuit system includes a processing integrated circuit die comprising a first die-to-die interface circuit and a memory interface circuit. The circuit system also includes a second integrated circuit die comprising a second die-to-die interface circuit and a compute circuit that performs computations for the processing integrated circuit die. The first and the second die-to-die interface circuits are coupled together. The compute circuit is coupled to exchange information with the memory interface circuit through the first and the second die-to-die interface circuits.
1 . A circuit system comprising:
a processing integrated circuit die comprising a first die-to-die interface circuit and a first memory interface circuit; and
a second integrated circuit die comprising a second die-to-die interface circuit and a compute circuit that performs computations for the processing integrated circuit die, wherein the first and the second die-to-die interface circuits are coupled together, and wherein the compute circuit is coupled to exchange information with the first memory interface circuit through the first and the second die-to-die interface circuits.
2 . The circuit system of claim 1 , wherein the second integrated circuit die further comprises an accelerator circuit that accelerates functions for the processing integrated circuit die, and wherein the accelerator circuit is coupled to exchange information with the first memory interface circuit through the first and the second die-to-die interface circuits.
3 . The circuit system of claim 1 further comprising:
an accelerator integrated circuit die comprising a third die-to-die interface circuit, wherein the processing integrated circuit die further comprises a fourth die-to-die interface circuit, wherein the third and the fourth die-to-die interface circuits are coupled together, and wherein the accelerator integrated circuit die is coupled to exchange information with the first memory interface circuit through the third and the fourth die-to-die interface circuits.
4 . The circuit system of claim 1 , wherein the compute circuit is configured to set up routing tables for connections for routing packets of data within the circuit system.
5 . The circuit system of claim 1 , wherein the processing integrated circuit die further comprises a second memory interface circuit, and wherein the compute circuit is coupled to exchange information with the second memory interface circuit through the first and the second die-to-die interface circuits.
6 . The circuit system of claim 1 , wherein the first memory interface circuit is configured to exchange signals with a memory device external to the processing integrated circuit die.
7 . The circuit system of claim 1 , wherein the processing integrated circuit die is a programmable logic integrated circuit.
8 . The circuit system of claim 1 , wherein the processing integrated circuit die is configured to accelerate storage virtualization functions and network virtualization functions.
9 . The circuit system of claim 1 , wherein the first and the second die-to-die interface circuits are coupled together through interconnects in one of an interposer, a package substrate, or an interconnection bridge in the circuit system.
10 . A method for sharing a first memory interface circuit in a processing integrated circuit die, comprising:
receiving first data from a first external memory device using the first memory interface circuit;
providing the first data from the first memory interface circuit to a compute circuit in a second integrated circuit die through a first die-to-die interface circuit in the processing integrated circuit die and through a second die-to-die interface circuit in the second integrated circuit die; and
performing computations with the compute circuit using the first data received from the processing integrated circuit die.
11 . The method of claim 10 further comprising:
receiving second data from a second external memory device using the first memory interface circuit;
providing the second data from the first memory interface circuit to an accelerator circuit in the second integrated circuit die through the first and the second die-to-die interface circuits; and
accelerating operations for the processing integrated circuit die with the accelerator circuit using the second data.
12 . The method of claim 10 further comprising:
receiving second data from the first external memory device using the first memory interface circuit;
providing the second data from the first memory interface circuit to an accelerator integrated circuit die through a third die-to-die interface circuit in the processing integrated circuit die and through a fourth die-to-die interface circuit in the accelerator integrated circuit die; and
accelerating operations for the processing integrated circuit die with the accelerator integrated circuit die using the second data.
13 . The method of claim 10 further comprising:
receiving additional data from a memory device external to the processing integrated circuit die using a second memory interface circuit in the processing integrated circuit die;
providing the additional data from the second memory interface circuit to the compute circuit through the first and the second die-to-die interface circuits; and
performing additional computations with the compute circuit using the additional data received from the processing integrated circuit die.
14 . The method of claim 10 , wherein performing the computations with the compute circuit using the first data further comprises:
setting up routing tables for connections for routing packets of data within a circuit system using the compute circuit.
15 . The method of claim 10 further comprising:
receiving second data from a second external memory device using a second memory interface circuit in the processing integrated circuit die;
providing the second data from the second memory interface circuit to an accelerator integrated circuit die through a third die-to-die interface circuit in the processing integrated circuit die and through a fourth die-to-die interface circuit in the accelerator integrated circuit die; and
accelerating operations for the processing integrated circuit die with the accelerator integrated circuit die using the second data.
16 . A circuit system comprising:
a processing integrated circuit die comprising a first die-to-die interface circuit, a first memory interface circuit, and a second memory interface circuit, wherein the first and the second memory interface circuits are adjacent to opposite sides of the processing integrated circuit die; and
an accelerator integrated circuit die that accelerates functions for the processing integrated circuit die, wherein the accelerator integrated circuit die comprises a second die-to-die interface circuit that is coupled to the first die-to-die interface circuit, and wherein the accelerator integrated circuit die is coupled to exchange information with the first and the second memory interface circuits through the first and the second die-to-die interface circuits.
17 . The circuit system of claim 16 , wherein the accelerator integrated circuit die and the processing integrated circuit die are mounted side-by-side in the circuit system.
18 . The circuit system of claim 16 , wherein the accelerator integrated circuit die and the processing integrated circuit die are vertically stacked in the circuit system.
19 . The circuit system of claim 16 , wherein the processing integrated circuit die is configured to perform storage virtualization functions or network virtualization functions.
20 . The circuit system of claim 16 , wherein each of the first and the second die-to-die interface circuits comprises input driver circuits and output driver circuits configured to transmit signals according to an interconnect protocol.