Freeze and clear logic circuits and methods for integrated circuits
An integrated circuit includes a programmable logic circuit and freeze circuitry coupled to receive a freeze signal and a control signal. The integrated circuit also includes a logic circuit coupled to receive an output signal of the programmable logic circuit. The logic circuit is also coupled to receive an output signal of the freeze circuitry. The freeze circuitry causes an output signal of the logic circuit to be in a predefined logic state in response to the freeze signal being asserted during power-up of the integrated circuit. The integrated circuit also includes clear circuitry that asserts the control signal in response to a clear signal being asserted after the power-up of the integrated circuit. The freeze circuitry causes the output signal of the logic circuit to be in the predefined logic state in response to the control signal being asserted.
1. An integrated circuit comprising:
a programmable logic circuit;
freeze logic circuitry comprising a first input coupled to receive a freeze signal and a second input coupled to receive a control signal;
second logic circuitry comprising a first input coupled to a first output of the programmable logic circuit and a second input coupled to an output of the freeze logic circuitry, wherein the freeze logic circuitry drives an output signal of the second logic circuitry to a predefined logic state in response to the freeze signal being asserted during power-up of the integrated circuit; and
clear logic circuitry that generates the control signal in response to a clear signal, wherein the freeze logic circuitry drives the output signal of the second logic circuitry to the predefined logic state in response to the control signal being asserted after the power-up of the integrated circuit.
2. The integrated circuit of claim 1 , wherein the freeze logic circuitry comprises a first logic gate circuit comprising an input coupled to receive the control signal, and wherein the freeze logic circuitry further comprises a second logic gate circuit that comprises a first input coupled to an output of the first logic gate circuit and a second input coupled to receive the freeze signal.
3. The integrated circuit of claim 2 , wherein the freeze logic circuitry further comprises a third logic gate circuit comprising an input coupled to receive the control signal, and wherein the freeze logic circuitry further comprises a fourth logic gate circuit that comprises a first input coupled to an output of the third logic gate circuit and a second input coupled to receive the freeze signal.
4. The integrated circuit of claim 3 further comprising:
fourth logic circuitry comprising a first input coupled to a second output of the programmable logic circuit and a second input coupled to an output of the fourth logic gate circuit, wherein the freeze logic circuitry drives an output signal of the fourth logic circuitry to the predefined logic state in response to the freeze signal being asserted during the power-up of the integrated circuit, and wherein the freeze logic circuitry drives the output signal of the fourth logic circuitry to the predefined logic state in response to the control signal being asserted after the power-up of the integrated circuit.
5. The integrated circuit of claim 4 , wherein the second logic circuitry comprises a NAND gate circuit, and wherein the fourth logic circuitry comprises a multiplexer circuit.
6. The integrated circuit of claim 1 , wherein the second logic circuitry is configurable to implement at least a portion of a bus of multiplexer circuits.
7. The integrated circuit of claim 1 , wherein the second logic circuitry comprises a NAND gate circuit.
8. The integrated circuit of claim 1 , wherein the second logic circuitry comprises a multiplexer circuit, and wherein the freeze logic circuitry controls an input of the multiplexer circuit.
9. The integrated circuit of claim 1 , wherein the clear logic circuitry comprises a multiplexer circuit configurable to select a value of the clear signal or a value of an additional clear signal to be provided in the control signal.
10. A method for controlling an output signal of a first logic circuit in an integrated circuit, the method comprising:
driving the output signal of the first logic circuit to a predefined logic state with freeze circuitry in response to a freeze signal being asserted during power-up of the integrated circuit;
controlling the output signal of the first logic circuit based on a first output signal of a programmable logic circuit after the power-up of the integrated circuit in response to the freeze signal being de-asserted;
asserting a control signal with clear logic circuitry in response to a clear signal after the power-up of the integrated circuit; and
driving the output signal of the first logic circuit to the predefined logic state with the freeze circuitry in response to the control signal being asserted.
11. The method of claim 10 further comprising:
driving an output signal of a second logic circuit to the predefined logic state with the freeze circuitry in response to the freeze signal being asserted during the power-up of the integrated circuit.
12. The method of claim 11 further comprising:
controlling the output signal of the second logic circuit based on a second output signal of the programmable logic circuit after the power-up of the integrated circuit in response to the freeze signal being de-asserted.
13. The method of claim 12 further comprising:
driving the output signal of the second logic circuit to the predefined logic state with the freeze circuitry in response to the control signal being asserted.
14. The method of claim 10 , wherein the freeze circuitry comprises a first logic gate circuit comprising an input coupled to receive the control signal, and wherein the freeze circuitry further comprises a second logic gate circuit that comprises a first input coupled to an output of the first logic gate circuit and a second input coupled to receive the freeze signal.
15. The method of claim 10 , wherein asserting the control signal with the clear logic circuitry further comprises selecting a value of the clear signal or a value of an additional clear signal with a multiplexer circuit in the clear logic circuitry to generate a value of the control signal.
16. An integrated circuit comprising:
a programmable logic circuit;
freeze circuitry coupled to receive a freeze signal and a control signal;
a first logic circuit coupled to receive a first output signal of the programmable logic circuit, wherein the first logic circuit is coupled to receive an output signal of the freeze circuitry, and wherein the freeze circuitry causes an output signal of the first logic circuit to be in a predefined logic state in response to the freeze signal being asserted during power-up of the integrated circuit; and
clear circuitry that asserts the control signal in response to a clear signal being asserted after the power-up of the integrated circuit, wherein the freeze circuitry causes the output signal of the first logic circuit to be in the predefined logic state in response to the control signal being asserted.
17. The integrated circuit of claim 16 further comprising:
a second logic circuit coupled to receive a second output signal of the programmable logic circuit, wherein the second logic circuit is coupled to receive the output signal of the freeze circuitry, and wherein the freeze circuitry causes an output signal of the second logic circuit to be in the predefined logic state in response to the freeze signal being asserted during the power-up of the integrated circuit.
18. The integrated circuit of claim 17 , wherein the freeze circuitry causes the output signal of the second logic circuit to be in the predefined logic state in response to the control signal being asserted.
19. The integrated circuit of claim 16 , wherein the clear circuitry comprises a multiplexer circuit configurable to select a value of the clear signal or a value of an additional clear signal to be provided as a value of the control signal.
20. The integrated circuit of claim 16 , wherein the freeze circuitry comprises a first logic gate circuit coupled to receive the control signal, and wherein the freeze circuitry further comprises a second logic gate circuit coupled to receive an output signal of the first logic gate circuit and the freeze signal.