Folded integer multiplication for field-programmable gate arrays

1. Folded integer multiplier (FIM) circuitry, comprising:

a multiplier configurable to perform multiplication;

a first addition/subtraction unit and a second addition/subtraction unit, both configurable to perform addition and subtraction, wherein the FIM circuitry is configurable to determine a plurality of products for a plurality of pairs of input values having a first number of bits, wherein the FIM circuitry is configurable to determine each product of the plurality of products by:

performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits, wherein the plurality of multiplication operations comprises a first number of multiplication operations and the multiplier is configurable to begin performing all multiplication operations of the plurality of multiplication operations within a first number of clock cycles equal to the first number of multiplication operations; and

performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction;

a first set of two registers configurable to receive and store first values generated by the multiplier from performing the plurality of multiplication operations;

a second set of two registers configurable to receive and store second values generated by the first addition/subtraction unit from performing a first portion of the plurality of operations involving addition or subtraction; and

a third set of registers configurable to receive and store third values generated by the second addition/subtraction unit from performing a second portion of the plurality of operations involving addition or subtraction.

2. The FIM circuitry of claim 1 , wherein the first and second addition/subtraction units are communicatively coupled to the first set of two registers and configurable to:

receive one or more of the first values; and

perform an operation of the plurality of operations involving addition or subtraction using the one or more of the first values.

3. The FIM circuitry of claim 1 , wherein the multiplier is communicatively coupled to a first register of the second set of two registers and configurable to:

receive one or more of the second values; and

perform a multiplication operation of the plurality of multiplication operations using the one or more of the second values.

4. The FIM circuitry of claim 3 , wherein the multiplier is not communicatively coupled to a second register of the second set of two registers.

5. The FIM circuitry of claim 1 , wherein the FIM circuitry is implemented on a programmable logic device.

6. The FIM circuitry of claim 5 , wherein the programmable logic device comprises a field-programmable gate array (FPGA).

7. The FIM circuitry of claim 6 , wherein the multiplier is implemented using hard logic of the FPGA, and the first and second addition/subtraction units are implemented using soft logic of the FPGA.

8. The FIM circuitry of claim 1 , wherein the multiplier is a 514-bit multiplier and each of the first and second addition/subtraction units is a 2052-bit addition/subtraction unit.

9. The FIM circuitry of claim 1 , further comprising control circuitry and a plurality of multiplexers, wherein the control circuitry is configurable to control the plurality of multiplexers to cause a first set of the values having fewer bits than the first number of bits to the multiplier.

10. The FIM circuitry of claim 1 , wherein the FIM circuitry is configurable to:

output a first product of the plurality of products; and

output a second product of the plurality of products the first number of clock cycles after outputting the first product.

11. An integrated circuit device, comprising:

programmable logic;

a multiplier configurable to perform multiplication;

a first addition/subtraction unit and a second addition/subtraction unit, both configurable to perform addition and subtraction, wherein the integrated circuit device is configurable to determine a plurality of products for a plurality of pairs of input values having a first number of bits, wherein the integrated circuit device is configurable to determine each product of the plurality of products by:

performing, using the multiplier, a plurality of multiplication operations involving values having fewer bits than the first number of bits, wherein the plurality of multiplication operations comprises a first number of multiplication operations and the multiplier is configurable to begin performing each multiplication operation of the plurality of multiplication operations in a first number of consecutive clock cycles equal to the first number of multiplication operations; and

performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction;

a first set of two registers configurable to receive and store first values generated by the multiplier from performing the plurality of multiplication operations;

a second set of two registers configurable to receive and store second values generated by the first addition/subtraction unit from performing a first portion of the plurality of operations involving addition or subtraction; and

a third set of registers configurable to receive and store third values generated by the second addition/subtraction unit from performing a second portion of the plurality of operations involving addition or subtraction.

12. The integrated circuit device of claim 11 , wherein:

the plurality of multiplication operations has a first number of total operations;

the plurality of operations involving addition or subtraction has a second number of total operations; and

a ratio of the second number of total operations to the first number of total operations is less than two.

13. The integrated circuit device of claim 12 , wherein:

the first number of total operations is nine; and

the second number of total operations is sixteen.

14. The integrated circuit device of claim 11 , wherein both the first addition/subtraction unit and the second addition/subtraction unit are configurable to begin performing the plurality of operations involving addition or subtraction prior to the multiplier beginning to perform the plurality of multiplication operations.

15. The integrated circuit device of claim 11 , wherein the multiplier is configurable to begin performing multiplication operations associated with a first pair of the plurality of pairs of input values while the first and second addition/subtraction units are performing addition operations associated with a second pair of the plurality of pairs of input values.

16. The integrated circuit device of claim 11 , wherein performing the plurality of operations involving addition or subtraction comprises performing addition involving two values having fewer bits than the first number of bits.

17. The integrated circuit device of claim 11 , wherein:

the first addition/subtraction unit is implemented using the programmable logic;

the second addition/subtraction unit is implemented using the programmable logic; or

both the first addition/subtraction unit and the second addition/subtraction unit are implemented using the programmable logic.

18. A field-programmable gate array (FPGA) comprising:

a multiplier configurable to perform multiplication;

a first addition/subtraction unit and a second addition/subtraction unit, both configurable to perform addition and subtraction;

a first set of registers configurable to store one or more products generated by the multiplier;

a second set of registers configurable to store one or more first values generated by the first addition/subtraction unit;

a third set of registers configurable to store one or more second values generated by the second addition/subtraction unit;

a first multiplexer communicatively coupled to the multiplier, wherein the first multiplexer is configurable to select a first received value as a first operand to provide to the multiplier based on a first control signal of a plurality of control signals;

a second multiplexer communicatively coupled to the multiplier, wherein the first multiplexer is configurable to select a second received value as a second operand to provide to the multiplier based on a second control signal of the plurality of control signals; and

control circuitry communicatively coupled to the first and second multiplexers, wherein the control circuitry is configurable to output the plurality of control signals to cause the FPGA to determine a plurality of products for a plurality of pairs of input values having a first number of bits, wherein the FPGA is configurable to determine each product of the plurality of products by:

performing, using the multiplier and based on the plurality of control signals, a plurality of multiplication operations involving values having fewer bits than the first number of bits, wherein the plurality of multiplication operations comprises a first number of multiplication operations and the multiplier is configurable to begin performing each multiplication operation of the plurality of multiplication operations in a sequence of consecutive clock cycles; and

performing, using the first and second addition/subtraction units, a plurality of operations involving addition or subtraction.

19. The FPGA of claim 18 , wherein the control circuitry is configurable to:

cause a sum stored in the second set of registers to be provided to the first multiplexer; and

cause the first multiplexer to output the sum to the multiplier.

20. The FPGA of claim 18 , wherein:

the first and second addition/subtraction units are implemented completely on programmable logic of the FPGA; and

the multiplier is implemented using DSP blocks of the FPGA.