Strict-sense minimal spanning switch non-blocking architecture
View Patent ↗The present invention discloses an apparatus to implement a m=n Non-Blocking Minimal Spanning Switch, where n=the total number of data input signals and m=the total number of data output signals and m=the number of crossbar connections in each switch. Data is input to the switch as a plurality of frames, whereby each crossbar connection contains a framer which detects framing patterns in the data. Skewed data is re-aligned and buffered so that the data output by each crossbar connection is equal and identical, thus any crossbar connection may be used to ensure a connection, eliminating the possibility of data interrupts.
1. An apparatus comprising:
a non-blocking minimal spanning switch comprising:
(a) receiver circuitry configured to receive a plurality of data transmitted as a plurality of frames across a plurality of transmitting lanes, wherein said plurality of data comprises n data input signals;
(b) a switch comprising m crossbar connections, wherein each of said n data input signals are input to each of said m crossbar connections, for a total of (m×n) switch input signals, wherein m=n, and wherein:
each of said m crossbar connections comprises (m×n) framers,
each of said (m×n) switch input signals are input to one of said (m×n) framers, and
said (m×n) framers determine a start of frame signal in each of said (m×n) switch input signals, said start of frame signal indicating the starting bit of each of said plurality of frames; and
(c) at least m multiplexers, wherein at least one of said m multiplexers is located within each of said m crossbar connections, whereby said m multiplexers selects data from one of said n data input signals and thereby outputs a single data output signal from each of said m crossbar connections, for a total of m switch output signals.
2. The apparatus of claim 1 , wherein each of said m crossbar connections further comprises (m×n) buffers, whereby each of said (m×n) framers employ said start of frame signal to re-align said (m×n) switch input signals and subsequently each of said (m×n) framers write said (m×n) switch input signals into a common input location of each of said (m×n) buffers, providing said (m×n) buffers with equal and identical (m×n) data output signals, thereby said m multiplexers select said m switch output signals from any of said (m×n) data output signals to output one of said m switch output signals from each of said m crossbar connections.
3. The apparatus of claim 2 , wherein each of said (m×n) buffers are First-In-First-Out (FIFO) buffers.
4. An apparatus comprising:
a non-blocking minimal spanning switch comprising:
(a) receiver circuitry configured to receive a plurality of data transmitted as a plurality of frames across a plurality of transmitting lanes, wherein said plurality of data comprises n trunk input signals;
(b) a switch comprising m crossbar connections, wherein each of said n trunk input signals are input to each of said m crossbar connections, for a total of (m×n) switch input signals, wherein m=n and wherein:
each of said m crossbar connections comprises (m×n) trunk framers,
each of said (m×n) trunk input signals are input to one of said (m×n) trunk framers, and
said (m×n) trunk framers determine a start of frame signal in each of said (m×n) trunk input signals, said start of frame signal indicating the starting bit of each of said plurality of frames; and
(c) at least m multiplexers, wherein at least one of said m multiplexers is located within each of said m crossbar connections, whereby said m multiplexers selects data from one of said n trunk input signals or, where said n trunk input signals are divided into X logical lanes, said m multiplexers selects data from one of said X logical lanes, thereby said m multiplexers output a single trunk output signal from each of said m crossbar connections, for a total of m switch output signals.
5. The apparatus of claim 4 , wherein said (m×n) trunk framers further comprise at least one de-multiplexer to divide each of said n trunk input signals into d logical data signals, whereby n×d=X, thereby providing a total of X logical lanes within each of said m crossbar connections.
6. The apparatus of claim 5 , wherein each of said m crossbar connections further comprises X buffers, whereby each of said (m×n) framers employ said start of frame signal to re-align said (m×n) switch input signals and subsequently each of said (m x n) framers, coupled to said de-multiplexers, write said X logical lanes into a common input location of each of said X buffers, providing said X buffers with equal and identical X logical output lanes, thereby said m multiplexers select said m switch output signals from any of said X logical lanes to output one of said m switch output signals from each of said m crossbar connections.
7. The apparatus of claim 6 , wherein each of said X buffers are First-In-First-Out (FIFO) buffers.
8. A method comprising:
(a) receiving, with a non-blocking minimal spanning switch, a plurality of data transmitted as a plurality of frames across a plurality of transmitting lanes, wherein said plurality of data comprises n data input signals;
(b) inputting each of said n data input signals to each of m crossbar connections of a switch, for a total of (m×n) switch input signals, wherein m=n and wherein:
each of said m crossbar connections comprises (m×n) trunk framers,
each of said (m×n) trunk input signals are input to one of said (m×n) trunk framers, and
said (m×n) trunk framers determine a start of frame signal in each of said (m×n) trunk input signals, said start of frame signal indicating the starting bit of each of said plurality of frames; and
(c) selecting, with at least one of m multiplexers, data from one of said n data input signals, and outputting a single data output signal from each of said m crossbar connections, for a total of m switch output signals, wherein:
at least one of said m multiplexers is located within each of said m crossbar connections; and
each of said m crossbar connections output equal and identical m output signals, thus said switch can select any of said m crossbar connections to ensure a connection.
9. The method of claim 8 , wherein each of said m crossbar connections further comprises a plurality of buffers, whereby each of said (m×n) framers employ said start of frame signal to re-align said (m×n) switch input signals and subsequently each of said (m×n) framers write said (m×n) switch input signals into a common input location of each of said plurality of buffers, providing said plurality of buffers with a plurality of data output signals, wherein said plurality of data output signals are equal and identical, thereby said m multiplexers select said m switch output signals from any of said plurality of data output signals to output one of said m switch output signals from each of said m crossbar connections.
10. The method of claim 9 , wherein said plurality of buffers are First-In-First-Out (FIFO) buffers.
11. The method of claim 8 , wherein said plurality of transmitting lanes are a plurality of serial data transmitting lanes or said plurality of transmitting lanes are a plurality of trunk transmitting lanes.
12. The method of claim 11 , wherein each of said plurality of trunk transmitting lanes are divided by at least one de-multiplexer into a plurality of logical lanes.