Chained command architecture for packet processing
Systems or methods of the present disclosure may include a programmable logic device having a first portion of programmable elements configured to implement a user logic. The programmable logic device also includes a second portion of the programmable elements. The second portion is configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines. The IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.
1 . A programmable logic device comprising:
a first portion of programmable elements configured to implement a user logic; and
a second portion of the programmable elements configured to implement an infrastructure processing unit (IPU) to enable the first portion of programmable elements to interface with a plurality of accelerator engines, wherein the IPU is to receive a chained command to cause two or more accelerator engines of the plurality of accelerator engines to perform sequential operations on a data packet in response to the chained command.
2 . The programmable logic device of claim 1 , wherein a subset of the second portion of the programmable elements are used to implement the two or more of the plurality of accelerator engines.
3 . The programmable logic device of claim 1 , wherein the two or more accelerator engines are arranged in a plurality of stages, wherein a first stage of the plurality of stages receives the data packet in response to the command.
4 . The programmable logic device of claim 3 , wherein receiving the data packet comprises reading the data packet from a packet data buffer.
5 . The programmable logic device of claim 4 , wherein a second stage of the plurality of stages receives the data packet from the first stage after a first operation corresponding to the stage is performed.
6 . The programmable logic device of claim 5 , wherein transmission of the data packet from the first stage to the second stage is performed without reading or writing data to the packet data buffer.
7 . The programmable logic device of claim 5 , wherein the first stage comprises one or more cyclic redundancy check engines.
8 . The programmable logic device of claim 7 , wherein a cyclic redundancy check engine of the cyclic redundancy check engines comprises cyclic redundancy check circuitry that performs cyclic redundancy computations on the packet.
9 . The programmable logic device of claim 8 , wherein the cyclic redundancy check engine of the cyclic redundancy check engines comprises checksum circuitry that validates an output of the cyclic redundancy check circuitry.
10 . The programmable logic device of claim 7 , wherein the second stage comprises a crypto engine to encrypt the packet received from the cyclic redundancy check engine.
11 . The programmable logic device of claim 1 , wherein the IPU makes a single write to a data packet buffer in response to the chained command.
12 . A programmable logic device comprising:
a device controller that transmits commands; and
a plurality of programming elements, wherein the plurality of programming elements is configured to implement:
user logic configured to perform operations based on a configuration loaded into the plurality of programming elements; and
an infrastructure processing unit (IPU) that is configured to implement a chained command architecture that is configured to perform multiple operations in multiple chained accelerator engines in response to a single command of the commands.
13 . The programmable logic device of claim 12 , wherein the plurality of programming elements are configured to implement the multiple chained accelerator engines.
14 . The programmable logic device of claim 13 , wherein the multiple chained accelerator engines are implemented in the infrastructure processing unit.
15 . The programmable logic device of claim 14 , wherein the multiple operations are performed using a single read and write to a packet data buffer.
16 . The programmable logic device of claim 12 , wherein the multiple operations are distributed among a plurality of sequential stages.
17 . The programmable logic device of claim 16 , wherein the sequential stages correspond to a defined order of operations.
18 . The programmable logic device of claim 17 , wherein the defined order of operations comprises a pre-cryptographic cyclic redundancy check operation then an encryption operation then a post-cryptographic cyclic redundancy check operation.
19 . A programmable fabric device having programmable elements comprising:
a first portion of the programmable elements configured to perform user-defined functions via a configuration loaded into the first portion of the programmable elements; and
a second portion of the programmable elements configured to implement an infrastructure processing unit that comprises a plurality of accelerator engines arranged sequentially in a chained command architecture that is to perform multiple operations in response to a single command, wherein performing the multiple operations comprises a single read to a data packet buffer and a single write to the data packet buffer.
20 . The programmable fabric device of claim 19 , wherein the second portion of the programmable elements is configured to disable at least some of the multiple operations for a subsequent command using a reconfiguration of the second portion of the programmable elements.