Soft network-on-chip overlay through a partial reconfiguration region

1. An integrated circuit device comprising:

a programmable logic fabric comprising programmable logic circuitry and a partial reconfiguration region; and

a network-on-chip (NOC) formed in soft logic of the integrated circuit device, wherein the NOC is configurable to remain operable during a partial reconfiguration of the partial reconfiguration region, wherein the NOC is a static overlay that is embedded inside the partial reconfiguration region.

2. The integrated circuit device of claim 1 , wherein the NOC comprises a plurality of specialized registers connected by a plurality of routing wires of the integrated circuit device.

3. The integrated circuit device of claim 2 , wherein each specialized register of the plurality of specialized registers comprises a register and a multiplexer.

4. The integrated circuit device of claim 3 , wherein each specialized register of the plurality of specialized registers is configurable to route data to the multiplexer without routing the data through the register.

5. The integrated circuit device of claim 1 , wherein the integrated circuit device comprises a field-programmable gate array (FPGA).

6. The integrated circuit device of claim 5 , wherein a first portion of the NOC transverses the partial reconfiguration region, wherein the first portion of the NOC is configured to transport date while the partial reconfiguration region undergoes the partial reconfiguration.

7. The integrated circuit device of claim 1 , comprising a second partial reconfiguration that is separated from the partial reconfiguration region by a static region of the programmable logic fabric.

8. The integrated circuit device of claim 1 , wherein the integrated circuit device is configurable to:

form a first data route from the partial reconfiguration region to the NOC when operating in a first mode; and

as a result of performing the partial reconfiguration, form a second data route from the partial reconfiguration region to the NOC.

9. An integrated circuit device comprising:

a programmable logic fabric comprising programmable logic circuitry, wherein the programmable logic fabric comprises a static region; and

a network-on-chip (NOC) formed in soft logic of the integrated circuit device and at least partially in the static region, and wherein the NOC comprises a plurality of specialized registers connected by a plurality of routing wires of the integrated circuit device.

10. The integrated circuit device of claim 9 , wherein the programmable logic fabric comprises a partial reconfiguration region, and wherein the NOC is implemented at least partially in the partial reconfiguration region.

11. The integrated circuit device of claim 10 , wherein the integrated circuit device is configurable to:

form a first data route from the partial reconfiguration region to the NOC when operating in a first mode; and

as a result of performing a partial reconfiguration operation, form a second data route from the partial reconfiguration region to the NOC.

12. The integrated circuit device of claim 10 , wherein the partial reconfiguration region comprises an input into the NOC or an output from the NOC.

13. The integrated circuit device of claim 9 , comprising a de-skew unit communicatively coupled to the NOC, wherein the de-skew unit is configured to de-skew an interface of the integrated circuit device.

14. The integrated circuit device of claim 13 , comprising a function block communicatively coupled to the de-skew unit.

15. The integrated circuit device of claim 9 , comprising an interface protocol communicatively coupled to the NOC.

16. The integrated circuit device of claim 9 , wherein each specialized register of the plurality of specialized registers comprises a register and a multiplexer, and wherein each specialized register of the plurality of specialized registers is configurable to route data to the multiplexer without routing the data through the register.

17. The integrated circuit device of claim 9 , comprising a plurality of partial reconfiguration regions that are separated by one or more static regions, wherein the NOC is disposed entirely within the one or more static regions.

18. A non-transitory computer-readable medium comprising instructions that, when executed, are configured to cause one or more processors to:

receive data regarding an integrated circuit and data regarding performance characteristics for a network-on-chip (NoC) to be designed;

generate a design for the NOC; and

generate instructions configured to cause circuitry corresponding to the NoC to be implemented on the integrated circuit, wherein when implemented on the integrated circuit, the NOC remains operational when a partial reconfiguration region undergoes a partial reconfiguration.

19. The non-transitory computer-readable medium of claim 18 , wherein the NOC is implemented in soft logic of the integrated circuit.

20. The non-transitory computer-readable medium of claim 18 , wherein the NOC is at least partially implemented in a partial reconfiguration region of the integrated circuit.