Aging-resistant signal path circuitry
View Patent ↗Systems and methods are related to selectively inverting circuit paths of an integrated circuit to reduce errors due to aging. An integrated circuit includes a first circuit path that receives an input signal and outputs a first output signal, a first selective inverter that receives the first output signal and outputs a first inverter output signal; and a second circuit path that receives the first selective inverter output signal and outputs a second output signal. In a first mode, the first selective inverter does not invert the first output signal and outputs the first output signal as the first selective inverter output signal. In a second mode, the first selective inverter inverts the first output signal and outputs an inverse of the first output signal as the first selective inverter output signal.
1. A system comprising:
a first circuit path, wherein the first circuit path is configured to age in a way that causes the first circuit path to introduce first signal errors; and
a second circuit path coupled in serial to the first circuit path, wherein the second circuit path is configured to age in a way that causes the second circuit path to introduce second signal errors, wherein the second signal errors are configured to counteract the first signal errors introduced by the first circuit path wherein, when the first circuit path and the second circuit path process a toggling signal configured to toggle between a first state of the toggling signal and a second state of the toggling signal:
the first signal errors comprise a dilation of the first state of the toggling signal and a contraction of the second state of the toggling signal; and
the second signal errors comprise a dilation of the second state of the toggling signal and a contraction of the first state of the toggling signal.
2. The system of claim 1 , wherein the first circuit path and the second circuit path process the toggling signal in a first mode of operation, wherein the first mode of operation comprises a data transfer mode and the toggling signal comprises a clock signal.
3. The system of claim 2 , wherein the data transfer mode comprises a double-data rate mode.
4. The system of claim 2 , wherein the first circuit path and the second circuit path process a static signal in a second mode of operation, wherein the second mode of operation comprises an idle mode.
5. The system of claim 4 , wherein the static signal comprises a logical LOW state to conserve power.
6. The system of claim 1 , wherein the first circuit path has a first number of active circuit elements that process a signal input to the first circuit path and the second circuit path has a second number of active circuit elements that process an additional signal output from the first circuit path, wherein the first number of active circuit elements is the same as the second number of active circuit elements.
7. The system of claim 1 , wherein the first circuit path and the second circuit path comprise active circuit elements, wherein the active circuit elements comprise inverters.
8. The system of claim 1 , wherein the toggling signal comprises a clock signal with a duty cycle of approximately 50%, and wherein the second signal errors are configured to counteract the first signal errors such that the duty cycle is within 3% of the 50%.
9. The system of claim 1 , wherein the second signal errors are configured to counteract the first signal errors such that after 10 years of aging, a duty cycle of the toggling signal varies no more than 1% from a non-aged integrated circuit.
10. The system of claim 1 , wherein the first signal errors comprise timing errors of a first polarity and the second signal errors comprise timing errors of a second polarity opposite the first polarity.
11. The system of claim 1 , wherein the dilation of the first state of the toggling signal is offset by the contraction of the first state of the toggling signal, and wherein the contraction of the second state of the toggling signal is offset by the dilation of the second state of the toggling signal.
12. The system of claim 1 , comprising an inverter configured to selectively invert signals passing from out of the first circuit path and into the second circuit path, wherein the inverter is configured to:
invert the signals when the first circuit path and the second circuit path are operating in the idle mode and wherein the inverter is configured not to invert the signals when the first circuit path and the second circuit path are not operating in the idle mode; or
invert the signals when the first circuit path and the second circuit path are not operating in the idle mode and wherein the inverter is configured to invert the signals when the first circuit path and the second circuit path are not operating in the idle mode.
13. The system of claim 12 , comprising a second inverter configured to selectively invert additional signals passing from out of the second circuit path, wherein the second inverter is configured to invert the additional signals to offset the inverting of the signals.
14. The system of claim 1 , wherein, when the first circuit path and the second circuit path process a static signal:
the first signal errors comprise a dilation of a first state of the static signal and a contraction of a second state of the static signal; and
the second signal errors comprise a dilation of the second state of the static signal and a contraction of the first state of the static signal.