Quick configurable universal register for a configurable integrated circuit die
An FPGA includes a number of logic elements in a core fabric. Each logic element includes a number of registers and each register includes a registered circuit path and a combinatorial circuit path. The registered and combinatorial circuit paths are in parallel. Each register includes a DFT circuit path that comprises an input in the registered circuit path and an output in the registered circuit path. The DFT circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path. Each register includes a CE time-borrowing circuit path. Each the CE time-borrowing circuit path includes an input in the registered circuit path and an output that is coupled to the input of the registered circuit path. The CE time-borrowing circuit path is not in series with the registered circuit path and is not in series with the combinatorial circuit path.
1. A circuit comprising:
a register that comprises a registered circuit path and a combinatorial circuit path, wherein the registered circuit path and the combinatorial circuit path are in parallel, and
a design for test (DFT) circuit path that comprises an input in the registered circuit path and an output in the registered circuit path,
wherein the registered circuit path comprises a first latch and a second latch that is in series with the first latch, wherein the input of the DFT circuit path is in a first feedback loop of the second latch, and wherein the output of the DFT circuit path is in a second feedback loop of the first latch.
2. The circuit of claim 1 , wherein the first feedback loop comprises a logic gate coupled to a buffer.
3. The circuit of claim 1 , wherein the second feedback loop comprises a buffer, a logic gate, and a passgate to hold a state of the first latch when the DFT circuit path is selected for operation.
4. The circuit of claim 1 , wherein the DFT circuit path comprises a passgate, and wherein the first latch comprises a logic gate.
5. The circuit of claim 1 , wherein the first feedback loop comprises a logic gate and a buffer to hold a state of the second latch when the DFT circuit path is selected for operation.
6. The circuit of claim 1 , wherein the combinatorial circuit path comprises a buffer coupled to a passgate.
7. The circuit of claim 1 , wherein the DFT circuit path comprises a buffer and a passgate.
8. The circuit of claim 1 , further comprising a clock enable (CE) time-borrowing circuit path, wherein the CE time-borrowing circuit path comprises an input in the registered circuit path and an output that is coupled to an input of the registered circuit path.
9. The circuit of claim 8 , wherein the CE time-borrowing circuit path comprises a buffer, a third latch, and a logic gate.
10. The circuit of claim 1 , wherein the register further comprises a logic gate that is coupled to an output of the second latch.
11. The circuit of claim 1 , wherein the circuit is in a field programmable gate array and the register is in a core fabric of the field programmable gate array.
12. A circuit comprising:
a register of a logic element, wherein the register comprises a registered circuit path and a combinatorial circuit path, and wherein the registered circuit path and the combinatorial circuit path are in parallel, and
a clock enable (CE) time-borrowing circuit path, wherein the CE time-borrowing circuit path comprises an input in the registered circuit path and an output that is coupled to an input of the registered circuit path.
13. The circuit of claim 12 , wherein the CE time-borrowing circuit path comprises a buffer, a latch, and a logic gate.
14. The circuit of claim 12 , further comprising:
a multiplexer coupled between the output of the CE time-borrowing circuit path and an input of the register.
15. The circuit of claim 12 , wherein the register further comprises a design for test (DFT) circuit path, wherein the registered circuit path comprises a first latch and a second latch coupled to the first latch, wherein an input of the DFT circuit path is in a first feedback loop of the second latch, and wherein an output of the DFT circuit path is in a second feedback loop of the first latch.
16. The circuit of claim 15 , wherein the DFT circuit path comprises a buffer and a passgate.
17. The circuit of claim 12 , wherein the combinatorial circuit path comprises a buffer coupled to a passgate.
18. The circuit of claim 12 , wherein the circuit is in a field programmable gate array and the logic element comprising the register is in a core fabric of the field programmable gate array.
19. An integrated circuit comprising:
a register that comprises a registered circuit path and a combinatorial circuit path, wherein the registered circuit path and the combinatorial circuit path are in parallel;
a design for test (DFT) circuit path that comprises an input in the registered circuit path and an output in the registered circuit path; and
a clock enable (CE) time-borrowing circuit path, wherein the CE time-borrowing circuit path comprises an input in the registered circuit path and an output that is coupled to an input of the registered circuit path.
20. The integrated circuit of claim 19 , wherein the registered circuit path comprises a first latch and a second latch that is in series with the first latch, the input of the DFT circuit path is in a first feedback loop of the second latch and the output of the DFT circuit path is in a second feedback loop of the first latch.