IP Library › Granted Patent US 12,717,548
Granted Patent B2
US 12,717,548 · App. 17/559,851 · Granted Aug 25, 2026

Embedded arithmetic blocks for structured ASICs

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Quick Facts
Patent No.
US 12,717,548
App. No.
17/559,851
Filed
Dec 22, 2021
Granted
Aug 25, 2026
Kind
B2
Art Unit
2151
USPC
708/235
Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 1, 2022
From: MENON, SANKARAN; LANGHAMMER, MARTIN; FANASWALLA, MUSTANSIR; SIMHA, KULDEEP
To: INTEL CORPORATION
Reel/Frame 059136/0496 →
Continuity (1)
Related Publication 20230195416A1 · Jun 22, 2023
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Hutton et al., “A Methodology for FPGA to Structured-ASIC Synthesis and Verification,” Proceedings of the Design Automation & Test in Europe Conference, Munich, Germany, 2006, pp. 1-6, doi: 10.1109/DATE.2006.243775. (Ye… [cited by examiner]