IP Library Granted Patent US 11,562,117
Granted Patent B2
US 11,562,117 · App. 17/337,824 · Granted Jan 24, 2023

Systems and methods for logic circuit replacement with configurable circuits

Inventors: Nij Dorairaj (Campbell, CA); David Kehlet (Los Altos Hills, CA)
Assignee: Intel Corporation
G06F30/343G06F21/14G06F30/327G06F30/347G06F30/392G06F30/394
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Quick Facts
Patent No.
US 11,562,117
App. No.
17/337,824
Granted
Jan 24, 2023
Kind
B2
Abstract

Methods and systems are provided for protecting a circuit design for an integrated circuit. Logic circuits are identified in at least a portion of the circuit design for replacement. The logic circuits in the circuit design are replaced with a bitstream and configurable circuits that comprise memory circuits. A transformed circuit design is generated for the integrated circuit that comprises the configurable circuits. The configurable circuits in the transformed circuit design perform logic functions of the logic circuits when the bitstream is stored in the memory circuits in the configurable circuits.

Claims (38)

1. A method for protecting a circuit design for an integrated circuit, the method comprising:

identifying logic circuits in at least a portion of the circuit design for replacement;

replacing the logic circuits in the circuit design with configurable circuits that comprise memory circuits in the integrated circuit;

generating a transformed circuit design for the integrated circuit that comprises the configurable circuits, wherein the configurable circuits in the transformed circuit design perform logic functions of the logic circuits when a bitstream is stored in the memory circuits and configures the configurable circuits;

evaluating whether the transformed circuit design exceeds a maximum amount of additional circuits allowed for the transformed circuit design; and

reducing an amount of circuits in the transformed circuit design to generate a modified transformed design having at most the maximum amount of the additional circuits if the transformed circuit design exceeds the maximum amount of the additional circuits.

2. The method of claim 1 , wherein the configurable circuits comprise lookup-table circuits.

3. The method of claim 2 , wherein each of the lookup-table circuits comprises a multiplexer circuit that selects at least one bit in response to input signals.

4. The method of claim 1 , wherein the configurable circuits comprise programmable finite state machine circuits.

5. The method of claim 1 , wherein identifying the logic circuits in at least the portion of the circuit design for replacement further comprises adjusting an amount of the logic circuits identified for replacement in the circuit design based on a complexity of the circuit design.

6. The method of claim 1 further comprising:

evaluating a metric for the transformed circuit design to determine if the transformed circuit design satisfies the metric; and

replacing additional logic circuits in the transformed circuit design with additional configurable circuits that comprise additional memory circuits using a constraint defined by the metric to generate a revised transformed circuit design for the integrated circuit if a determination is made that the transformed circuit design does not achieve the metric.

7. The method of claim 6 , wherein evaluating the metric for the transformed circuit design to determine if the transformed circuit design satisfies the metric further comprises determining if the bitstream is able to be reverse engineered using a known reverse engineering technique or known attack.

8. The method of claim 1 further comprising:

performing synthesis, placement, and routing of the transformed circuit design on the integrated circuit.

9. The method of claim 1 further comprising:

storing the bitstream in the memory circuits in the integrated circuit to configure the configurable circuits to perform the logic functions of the logic circuits.

10. A non-transitory computer-readable storage medium comprising instructions stored thereon for causing a computer to execute a method for protecting a circuit design for an integrated circuit, the method comprising:

identifying logic circuits that perform logic functions in at least a portion of the circuit design for replacement;

replacing the logic circuits in the circuit design with configurable circuits that perform the logic functions of the logic circuits when a bitstream is stored in memory circuits in the configurable circuits and used to configure the configurable circuits to generate a transformed circuit design for the integrated circuit, wherein the transformed circuit design comprises the configurable circuits;

evaluating whether the transformed circuit design exceeds a maximum amount of additional circuits allowed for the transformed circuit design; and

reducing an amount of circuits in the transformed circuit design to generate a modified transformed design having at most the maximum amount of the additional circuits if the transformed circuit design exceeds the maximum amount of the additional circuits.

11. The non-transitory computer-readable storage medium of claim 10 , wherein the configurable circuits comprise lookup-table circuits.

12. The non-transitory computer-readable storage medium of claim 10 , wherein the configurable circuits comprise programmable finite state machine circuits.

13. The non-transitory computer-readable storage medium of claim 10 , wherein identifying the logic circuits that perform the logic functions in at least the portion of the circuit design for replacement further comprises adjusting an amount of the logic circuits identified for replacement in the circuit design based on a complexity of the circuit design.

14. The non-transitory computer-readable storage medium of claim 10 , wherein the method further comprises:

evaluating a metric for the transformed circuit design to determine if the transformed circuit design satisfies the metric; and

replacing additional logic circuits in the transformed circuit design with additional configurable circuits that comprise additional memory circuits using a constraint defined by the metric to generate a revised transformed circuit design for the integrated circuit if a determination is made that the transformed circuit design does not satisfy the metric.

15. The non-transitory computer-readable storage medium of claim 14 , wherein evaluating the metric for the transformed circuit design to determine if the transformed circuit design satisfies the metric further comprises determining if the bitstream is able to be reverse engineered using a known reverse engineering technique or known attack.

16. A computer system configured to protect a circuit design for an integrated circuit, the computer system comprising:

a logic circuit replacement tool for identifying logic circuits that perform logic functions for replacement in at least a portion of the circuit design,

wherein the logic circuit replacement tool generates a transformed circuit design for the integrated circuit by replacing the logic circuits in the circuit design with configurable circuits that perform the logic functions of the logic circuits when a bitstream is stored in memory circuits in the configurable circuits and used to configure the configurable circuits, wherein the transformed circuit design comprises the configurable circuits; and

wherein the logic circuit replacement tool evaluates whether the transformed circuit design exceeds a maximum amount of additional circuits allowed for the transformed circuit design, and reduces an amount of circuits in the transformed circuit design to generate a modified transformed design having at most the maximum amount of the additional circuits if the transformed circuit design exceeds the maximum amount of the additional circuits.

17. The computer system of claim 16 , wherein the configurable circuits comprise programmable finite state machine circuits.

18. The computer system of claim 16 , wherein the configurable circuits comprise lookup-table circuits.

19. The computer system of claim 16 , wherein the logic circuit replacement tool adjusts an amount of the logic circuits identified for replacement in the circuit design based on a complexity of the circuit design.

20. The computer system of claim 16 , wherein the logic circuit replacement tool evaluates a metric for the transformed circuit design to determine if the transformed circuit design satisfies the metric.

Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 3, 2021
From: DORAIRAJ, NIJ; KEHLET, DAVID
To: INTEL CORPORATION
Reel/Frame 056429/0865 →
Continuity (1)
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