Semiconductor device including a redistribution layer and metallic pillars coupled thereto

1. A semiconductor device, comprising:

a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells forming an L-DMOS device and a P-LDMOS device;

a redistribution layer electrically coupled to said plurality of LDMOS cells and configured to provide a common circuit node for a drain region of said N-LDMOS device and said P-LDMOS device;

a plurality of metallic pillars distributed over and electrically coupled to said redistribution layer; and

a conductive patterned leadframe electrically coupled to said redistribution layer by said plurality of metallic pillars, wherein portions of said conductive patterned leadframe are exposed to serve as external contacts, and a drain region external contact of said portions of said conductive patterned leadframe entirely overlies a footprint of the drain region of said N-LDMOS device and said P-LDMOS device.

2. The semiconductor device as recited in claim 1 , further comprising a plurality of gate drivers electrically coupled to said redistribution layer and to gates of said plurality of LDMOS cells.

3. The semiconductor device as recited in claim 1 , wherein said semiconductor device is potted with an encapsulate.

4. The semiconductor device as recited in claim 1 , wherein ones of said external contacts are configured to be coupled to a printed circuit board.

5. The semiconductor device as recited in claim 4 , wherein ones of said external contacts are configured to be coupled to a plurality of decoupling devices on said printed circuit board.

6. The semiconductor device as recited in claim 4 , wherein ones of said external contacts are configured to be coupled to a plurality of decoupling devices through vias on an opposing surface of said printed circuit board.

7. The semiconductor device as recited in claim 6 , wherein said at least one of said plurality of decoupling devices is located under said semiconductor die.

8. The semiconductor device as recited in claim 1 , wherein ones of said external contacts are coupled to a plurality of gate drivers electrically coupled to said redistribution layer and to gates of said plurality of LDMOS cells.

9. The semiconductor device as recited in claim 1 , wherein said plurality of metallic pillars comprises copper.

10. The semiconductor device as recited in claim 1 , wherein said plurality of metallic pillars is formed as electroplated columns.

11. The semiconductor device as recited in claim 1 , further comprising a metallic layer formed below said redistribution layer including a plurality of alternating source and drain metallic strips formed above a substrate of said semiconductor die and parallel to and forming an electrical contact with respective ones of source regions and said drain region of said N-LDMOS device and said P-LDMOS deivice.

12. A method of forming a semiconductor device, comprising:

forming a plurality of laterally diffused metal oxide semiconductor (LDMOS) cells of an LDMOS device in a semiconductor die;

coupling a redistribution layer to said plurality of LDMOS cells;

distributing over and coupling a plurality of metallic pillars to said redistribution layer; and

coupling a plurality of gate drivers to said redistribution layer and to gates of said plurality of LDMOS cells, wherein said plurality of gate drivers are positioned on a periphery of said semiconductor die.

13. The method as recited in claim 12 , further comprising:

coupling a conductive patterned leadframe to said redistribution layer by said plurality of metallic pillars; and

potting said semiconductor device with an encapsulant, wherein portions of said conductive patterned leadframe are exposed to serve as external contacts for said semiconductor device.

14. The method as recited in claim 13 , wherein ones of said external contacts are coupled to said plurality of gate drivers coupled to said redistribution layer and to gates of said plurality of LDMOS cells.

15. The method as recited in claim 13 , wherein ones of said external contacts are coupled to drains or sources of said plurality of LDMOS cells through said redistribution layer.

16. The method as recited in claim 12 , further comprising forming a metallic layer below said redistribution layer including a plurality of alternating source and drain metallic strips formed above a substrate of said semiconductor die and parallel to and forming an electrical contact with respective ones of a plurality of source and drain regions of said LDMOS device.

17. A semiconductor device, comprising:

a semiconductor die formed with a plurality of laterally diffused metal oxide semiconductor (LDMOS) cell forming an N-LDMOS device and a P-LDMOS device;

a redistribution layer electrically coupled to said plurality of LDMOS cells and configured to provide a common circuit node for drain regions of said N-LDMOS device and said P-LDMOS device;

a plurality of metallic pillars distributed over and electrically coupled to said redistribution layer; and

a plurality of gate drivers electrically coupled to said redistribution layer and to gates of said plurality of LDMOS cells, wherein said plurality of gate drivers are positioned on a periphery of said semiconductor die.

18. The semiconductor device as recited in claim 17 further comprising a conductive patterned leadframe electrically coupled to said redistribution layer by said plurality of metallic pillars.

19. The semiconductor device as recited in claim 18 , wherein said semiconductor device is potted with encapsulant.

20. The semiconductor device as recited in claim 18 , wherein portions of said conducitve patterned leadframe are exposed to serve as external contacts for said semidonductor device.