Circuits And Methods For Multi-Layered Networks
An integrated circuit includes a core region of logic circuits and a network routed outside the core region. The network includes a wide layer and a narrow layer. The wide layer comprises first routers coupled in series. The narrow layer comprises second routers coupled in series.
1 . An integrated circuit comprising:
a core region of logic circuits; and
a network routed outside the core region and comprising a wide layer and a narrow layer, wherein the wide layer comprises first routers coupled in series, and wherein the narrow layer comprises second routers coupled in series.
2 . The integrated circuit of claim 1 , wherein the narrow layer is routed alongside the wide layer.
3 . The integrated circuit of claim 1 , wherein the core region further comprises bridge circuits coupled to the first routers and to the second routers.
4 . The integrated circuit of claim 1 further comprising:
control circuits coupled to the first routers and to the second routers.
5 . The integrated circuit of claim 1 , wherein the wide layer is configured to route a header, control information, and data.
6 . The integrated circuit of claim 1 , wherein the narrow layer is configured to route control information and a header without data.
7 . The integrated circuit of claim 1 , wherein the wide layer is configurable to route write requests, responses to read requests, and wide streaming communication packets.
8 . The integrated circuit of claim 1 , wherein the narrow layer is configurable to route read requests, responses to write requests, and narrow streaming communication packets.
9 . The integrated circuit of claim 1 , wherein the integrated circuit is a configurable logic integrated circuit, and wherein the logic circuits are configurable logic circuits.
10 . A method for routing packets through a network in an integrated circuit, the method comprising:
providing first control information and data through a wide layer of the network between a first circuit in a core region of the integrated circuit and a second circuit in a peripheral region of the integrated circuit; and
providing second control information through a narrow layer of the network between a third circuit in the core region and a fourth circuit in the peripheral region.
11 . The method of claim 10 , wherein providing the first control information and the data through the wide layer comprises providing one of the packets comprising memory addresses, routing information, and the data through the wide layer.
12 . The method of claim 10 , wherein providing the second control information through the narrow layer comprises providing one of the packets comprising memory addresses and routing information through the narrow layer without the narrow layer comprising bandwidth to route additional data.
13 . The method of claim 10 further comprising performing clock crossing, data rate matching, encoding, and decoding at the first circuit for the first control information and the data.
14 . The method of claim 10 further comprising performing clock crossing, data rate matching, encoding, and decoding at the third circuit for the second control information.
15 . The method of claim 10 , wherein the network is routed around a periphery of the core region.
16 . A network in an integrated circuit, wherein the network comprises:
a wide layer comprising first routers configurable to route data bits and control bits between a first source circuit and a first destination circuit; and
a narrow layer comprising second routers configurable to route control bits between a second source circuit and a second destination circuit.
17 . The network of claim 16 , wherein the first routers are coupled in a first ring configuration around a core region of the integrated circuit, and wherein the second routers are coupled in a second ring configuration around the core region.
18 . The network of claim 16 , wherein the second routers are configurable to route the control bits without routing additional data bits between the second source circuit and the second destination circuit.
19 . The network of claim 16 , wherein at least one of the first source circuit, the second source circuit, the first destination circuit, or the second destination circuit is a bridge circuit in a core region of the integrated circuit.
20 . The network of claim 16 , wherein at least one of the first source circuit, the second source circuit, the first destination circuit, or the second destination circuit is a control circuit in a peripheral region of the integrated circuit.