Method and apparatus for supporting temporal virtualization on a target device
View Patent ↗A method for designing a system on a target device includes modifying a circuit to enable the circuit to support a plurality of threads at an instant of time. An interface is generated that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein at least one of the modifying and the generating is performed by a processor.
1. A method for designing a system on a target device, comprising:
modifying a circuit to enable the circuit to support a plurality of threads at a same time; and
generating an interface that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein the interface prevents data associated with a thread that is swapped out to be utilized by another thread, wherein at least one of the modifying and the generating is performed by a processor;
generating a data file that describes the system that includes the modified circuit and the interface; and
programming the target device with the data file to physically transform components on the target device to implement the system.
2. The method of claim 1 , wherein modifying the circuit comprises adding C-1 registers before each register in a feedback path or a reconvergent fanout in the circuit, wherein C is the number of threads to be supported by the circuit.
3. The method of claim 1 , wherein generating the interface comprises:
generating input multiplexers having C inputs, wherein C is a number of threads to be supported by the circuit;
generating output demultiplexers having C outputs; and
generating a scheduler that selects the input multiplexers and output demultiplexers.
4. The method of claim 3 , wherein generating the interface further comprises generating demultiplexers for capturing output of each state in the circuit.
5. The method of claim 3 , wherein generating the interface further comprises generating multiplexers for enabling data for a thread to be swapped into one or more states in the circuit.
6. The method of claim 3 , wherein the scheduler clears data in one or more registers associated with a thread that is swapped out.
7. The method of claim 1 , wherein the one or more threads that are swapped out of the execution queue and the one or more other threads are swapped into the execution queue in response to an evaluation of a priority of the threads.
8. The method of claim 1 , wherein the modifying and generating are performed during synthesis prior to placement and routing during hardware description language compilation.
9. The method of claim 1 , wherein the circuit and interface are implemented on the target device.
10. The method of claim 1 , wherein modifying the circuit comprises adding C-1 memory systems, wherein C is a number of threads to be supported by the circuit and data is serialized in and out of the C-1 memory systems.
11. The method of claim 10 , wherein modifying the circuit comprises adding a component to stall the system to allow the data to be serialized in and out of the C-1 memory systems.
12. The method of claim 1 further comprising:
identifying the circuit to be modified to support the plurality of threads at a same time; and
identifying the plurality threads.
13. The method of claim 12 , wherein identifying the circuit comprises receiving input provided by a designer identifying the circuit.
14. The method of claim 12 , wherein identifying the circuit comprises evaluating a high-level design of the system.
15. The method of claim 12 , wherein identifying the number of threads comprises receiving input provided by a designer identifying the number.
16. The method of claim 12 , wherein identifying the number of threads comprises evaluating a high-level design of the system.
17. A system designer, comprising
a synthesis unit that includes a circuit transformation unit that modifies a circuit to enable the circuit to support a plurality of threads at a same time, and an interface generation unit that generates an interface that enables one or more of the plurality of threads to be swapped out of an execution queue for accessing the circuit and that enables one or more other threads to be swapped into the execution queue for accessing the circuit, wherein the interface prevents data associated with a thread that is swapped out to be utilized by another thread; and
an assembly unit that generates a data file that describes a system that includes the modified circuit and the interface, and that programs the target device with the data file to physically transform components on the target device to implement the system, wherein at least one of the synthesis unit and assembly unit is implemented with a processor.
18. The system designer of claim 17 , wherein the circuit transformation unit modifies the circuit by adding C-1 registers before each register in a feedback path or a reconvergent fanout in the circuit, wherein C is a number of threads to be supported by the circuit.