Stacked programmable integrated circuitry with smart memory
View Patent ↗Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. The programmable coarse-grain routing network and smart memory circuitry may be implemented on an active interposer die. the smart memory circuitry may be configured to perform higher level functions than simple read and write operations. The smart memory circuitry may carry out command based low cycle count operations using a state machine without requiring execution of a program code, complex microcontroller based multicycle operations, and other non-generic microcontroller based smart RAM functions.
1. A multichip package, comprising:
a package substrate;
an active interposer mounted on the package substrate; and
an integrated circuit mounted on the active interposer, wherein the active interposer comprises:
a programmable coarse-grain routing network having a plurality of channels forming a deterministic routing path with guaranteed timing closure; and
smart memory circuitry configured to perform a plurality of different memory operations that include higher level functions than simple read and write memory access.
2. The multichip package of claim 1 , wherein the smart memory circuitry comprises a state machine configured to perform a sequence of command based operations without execution of a program code.
3. The multichip package of claim 2 , wherein the smart memory circuitry comprises microcontroller circuitry configured to perform more complex operations than the command based operations associated with the state machine.
4. The multichip package of claim 2 , wherein the command based operations performed by the state machine comprise operations selected from the group consisting of: a data update, a data comparison, and a linked list traversal.
5. The multichip package of claim 2 , wherein smart memory circuitry is implemented as content addressable memory (CAM) using the state machine.
6. The multichip package of claim 2 , wherein smart memory circuitry is implemented as cache memory using the state machine.
7. The multichip package of claim 3 , wherein the complex operations performed by the smart memory circuitry comprise operations selected from the group consisting of: a data arrangement and a linked list traversal.
8. The multichip package of claim 3 , wherein smart memory circuitry is implemented as a direct memory access (DMA) controller using the microcontroller circuitry.
9. The multichip package of claim 3 , wherein the integrated circuit die comprises logic fabric circuitry, and wherein the microcontroller circuitry is configured to generate control signals for the logic fabric circuitry on the integrated circuit die.
10. The multichip package of claim 1 , wherein the smart memory circuitry comprises a plurality of random-access memory (RAM) blocks that can be composed into memory of variable width and depth.
11. The multichip package of claim 1 , wherein the integrated circuit die comprises an array of logic fabric sectors, and wherein the smart memory circuitry comprises an array of smart memory sectors spatially corresponding to the array of logic fabric sectors.
12. The multichip package of claim 11 , wherein the array of logic fabric sectors comprises a first group of input-output driver circuits, and wherein the array of smart memory sectors comprises a second group of input-output driver circuits aligned to the first group of input-output driver circuits.
13. The multichip package of claim 11 , wherein each smart memory sector in the array of smart memory sectors comprises a plurality of smart random-access memory (RAM) blocks interconnected by the programmable coarse-grain routing network.
14. The multichip package of claim 13 , wherein the smart RAM blocks are interconnected using an array of configurable 4-port connection box circuits.
15. The multichip package of claim 14 , wherein the smart PRA blocks are connected to the programmable coarse-grain routing network via a plurality of configurable 3-port switch box circuits.
16. The multichip package of claim 13 , wherein the active interposer further comprises at least one dedicated function intellectual property (IP) block embedded within plurality of smart RAM blocks.
17. The multichip package of claim 16 , wherein the dedicated function IP block comprises a hardened block selected from the group consisting of: a protocol bridge and global routing control block, a global routing buffer block, a direct memory access block, and a microcontroller.
18. Circuitry, comprising:
a plurality of programmable logic fabric sectors; and
a plurality of smart memory sectors formed directly under the plurality of programmable logic fabric sectors, wherein each smart memory sector in the plurality of smart memory sectors comprises an array of smart random-access memory (RAM) blocks, and at least one smart RAM block in the array of smart RAM blocks comprises:
a state machine configured to perform operations at a first speed; and
microcontroller circuitry configured to perform operations at a second feed slower than the first speed.
19. The circuitry of claim 18 , wherein the microcontroller circuitry comprises a program counter, a link register, an instruction decoder, and an arithmetic logic unit.
20. The circuitry of claim 18 , wherein the at least one smart RAM block further comprises:
an address register configured to store a local address;
an address input configured to receive an address signal; and
a comparison circuit configured to compare the value of the address signal to the stored local address.
21. The circuitry of claim 18 , wherein the at least one smart RAM block further comprises a counter configured to support programmable burst lengths in response to commands requiring a streaming response.
22. The circuitry of claim 18 , wherein the at least one smart RAM block further comprises a priority encoder 1012 configured to support content addressable memory (CAM) operations to extract address values for matching data words.
23. The circuitry of claim 18 , wherein the at least one smart RAM block further comprises a power manager configured to manage the power state of the at least one smart RAM block.
24. An apparatus, comprising:
an active interposer; and
a field-programmable gate array (FPGA) die mounted on the active interposer, wherein the active interposer comprises:
smart memory circuitry comprises random-access memory (RAM) blocks composable into different widths and depths and a state machine configured to drive a sequence of operations without having to execute a microcontroller program code.