Apparatus and method of voltage regulation control for integrated circuit
One embodiment relates to a method of controlling supply voltage regulation within an integrated circuit. An external interrupt is sent from an external interaction processing layer to a processor in the integrated circuit. Off-die instructions are generated by the external interaction processing layer and sent to the processor. The off-die instructions are executed by the processor to test and adjust supply voltage regulation within the integrated circuit on a sector-by-sector basis. Another embodiment relates to a method of controlling a supply voltage regulator for a sector of an integrated circuit. Commands are sent by a processor and translated by a sector manager to bits. The bits are loaded into registers so as to set the regulator control circuit to the testing mode send a supply voltage to an analog-to-digital converter. Other embodiments and features are also disclosed.
1. An integrated circuit comprising:
a first sector manager circuit that manages a first sector of the integrated circuit;
a test control register that receives a first set of bits from the first sector manager circuit;
a first supply voltage regulator for the first sector;
a second supply voltage regulator for a second sector of the integrated circuit;
a first multiplexor in a first regulator control circuit; and
a second multiplexor in a second regulator control circuit,
wherein a first output of the test control register is coupled to a first input of the first multiplexor via a control line, wherein a second input of the first multiplexor is coupled to an analog supply voltage output of the first supply voltage regulator, wherein a third input of the first multiplexor is coupled to an output of the second multiplexor, and wherein a first input of the second multiplexor is coupled to an analog supply voltage output of the second supply voltage regulator.
2. The integrated circuit of claim 1 , wherein the first sector manager circuit asserts an analog test control signal that enables the first set of bits to be loaded into the test control register.
3. The integrated circuit of claim 1 , further comprising:
a voltage trimming register that receives a second set of bits from the first sector manager circuit,
wherein the second set of bits in the voltage trimming register controls adjustment of a voltage level of the analog supply voltage output of the first supply voltage regulator.
4. The integrated circuit of claim 3 , wherein the first and second sets of bits are loaded serially to the test control register and the voltage trimming register, respectively.
5. The integrated circuit of claim 1 , further comprising:
a processor;
a second sector manager circuit that manages the second sector of the integrated circuit and that receives commands from the processor; and
a processor network connecting the processor to the first and second sector manager circuits,
wherein the first and second regulator control circuits comprise the first and second sector manager circuits for the respective first and second sectors of the integrated circuit.
6. The integrated circuit of claim 1 further comprising:
a voltage analog-to-digital converter, wherein an output of the first multiplexor is coupled to an input of the voltage analog-to-digital converter.
7. The integrated circuit of claim 1 , wherein the first regulator control circuit further comprises a first voltage trimming register, wherein an output of the first voltage trimming register is coupled to an input of the first supply voltage regulator, wherein the second regulator control circuit further comprises a second voltage trimming register, and wherein an output of the second voltage trimming register is coupled to an input of the second supply voltage regulator.
8. The integrated circuit of claim 1 , wherein the test control register is coupled via a selection line to the first supply voltage regulator.
9. An integrated circuit comprising:
a first sector manager circuit that manages a first sector of the integrated circuit;
a first regulator control circuit comprising a test control register and a first multiplexor, wherein the test control register receives a first set of bits from the first sector manager circuit;
a first supply voltage regulator for the first sector;
a second supply voltage regulator for a second sector of the integrated circuit; and
a second regulator control circuit comprising a second multiplexor, wherein a first input of the first multiplexor is coupled to the test control register via a control line, wherein a second input of the first multiplexor is coupled to a supply voltage output of the first supply voltage regulator, wherein an output of the first multiplexor is coupled to a first input of the second multiplexor, and wherein a second input of the second multiplexor is coupled to a supply voltage output of the second supply voltage regulator.
10. The integrated circuit of claim 9 further comprising:
a processor circuit that provides commands to the first sector manager circuit.
11. The integrated circuit of claim 10 , wherein the processor circuit processes a digital reading of a supply voltage generated by the first supply voltage regulator to generate a decision instruction and provides the decision instruction to the first sector manager circuit.
12. The integrated circuit of claim 11 , wherein the first regulator control circuit further comprises:
a voltage trimming register, and wherein the first sector manager circuit translates the decision instruction to a second set of bits and loads the second set of bits into the voltage trimming register and the test control register.
13. The integrated circuit of claim 12 , wherein the voltage trimming register adjusts a voltage level of the supply voltage based on a first plurality of the second set of bits stored in the voltage trimming register.
14. The integrated circuit of claim 13 , wherein the test control register resets the first regulator control circuit to a normal operating mode based on a second plurality of the second set of bits in the test control register.
15. The integrated circuit of claim 9 further comprising:
a voltage analog-to-digital converter, wherein an output of the second multiplexor is coupled to an input of the voltage analog-to-digital converter.
16. The integrated circuit of claim 9 , wherein the first regulator control circuit further comprises:
a voltage trimming register that receives a second set of bits from the first sector manager circuit, and wherein the second set of bits in the voltage trimming register controls adjustment of a voltage level of the supply voltage output of the first supply voltage regulator.
17. The integrated circuit of claim 9 , wherein the second regulator control circuit further comprises an additional test control register coupled to a third input of the second multiplexor.
18. The integrated circuit of claim 9 further comprising:
a processor;
a second sector manager circuit managing the second sector of the integrated circuit and receiving commands from the processor; and
a processor network connecting the processor to the first and second sector manager circuits.