Device under test board with offset connection to host board

1. A circuit board, comprising:

a first edge connector configured to communicatively couple the circuit board to a first connector of a second circuit board, wherein the first edge connector extends from a side of the circuit board a first length; and

a second edge connector configured to communicatively couple the circuit board to a second connector of the second circuit board, wherein the second edge connector extends from the side of the circuit board a second length that is different than the first length, wherein the first edge connector and the second edge connector extend from the same side of the circuit board, and wherein the first edge connector is offset from the second edge connector by a recession, wherein the first edge connector and the second edge connector terminate in different planes.

2. The circuit board of claim 1 , wherein the circuit board comprises a device under test (DUT) board configured to receive a device under test, wherein the device under test comprises an integrated circuit.

3. The circuit board of claim 2 , wherein the integrated circuit comprises a programmable logic device.

4. The circuit board of claim 3 , wherein the programmable logic device comprises a field-programmable gate array (FPGA).

5. The circuit board of claim 1 , wherein:

the first edge connector is configured to provide a first number of data lanes;

the second edge connector is configured to provide a second number of data lanes; and

the first and second numbers of data lanes are different.

6. The circuit board of claim 1 , wherein:

the first edge connector comprises a first peripheral component interconnect express (PCIe) connector; and

the second edge connector comprises a second PCIe connector.

7. The circuit board of claim 6 , wherein:

the first PCIe connector comprises a PCIe x16 connector; and

the second PCIe connector comprises a PCIe x8 connector.

8. The circuit board of claim 1 , wherein:

the first edge connector comprises a peripheral component interconnect express (PCIe) connector; and

the second edge connector comprises a connector other than a PCIe connector.

9. The circuit board of claim 1 , wherein the recession is equal to a difference between the first length and the second length, wherein the recession measures 2.0 to 7.5 millimeters.

10. The circuit board of claim 9 , wherein the recession measures 4.0 to 5.0 millimeters.

11. The circuit board of claim 1 , wherein the second edge connector comprises a test-coupon that is removable from the circuit board.

12. A system comprising:

a first circuit board comprising:

a first connector configured to receive an edge connector; and

a second connector configured to receive a different edge connector; and

a second circuit board comprising:

a first edge connector configured to communicatively couple the second circuit board to the first circuit board, wherein the first edge connector extends from a side of the second circuit board by a first length; and

a second edge connector configured to communicatively couple the second circuit board to the first circuit board, wherein the second edge connector extends from the side of the second circuit board by a second length that is different than the first length, wherein the first edge connector and the second edge connector extend from the same side of the second circuit board, and wherein the first edge connector is offset from the second edge connector based on a difference between the first length and the second length.

13. The system of claim 12 , wherein the second circuit board comprises a device under test (DUT) board configured receive a device under test, wherein the device under test comprises a programmable logic device.

14. The system of claim 13 , wherein:

the first connector comprises a first right-angle connector; and

the second connector comprises a second right-angle connector.

15. The system of claim 13 , wherein the second circuit board is configured to be connected substantially orthogonal to the first circuit board when the first edge connector is inserted into the first connector and the second edge connector is inserted into the second connector.

16. The system of claim 13 , wherein the programmable logic device comprises a field-programmable gate array (FPGA).

17. The system of claim 12 , wherein:

the first edge connector comprises a first peripheral component interconnect express (PCIe) connector; and

the second edge connector comprises a second PCIe connector.

18. The system of claim 17 , wherein the first PCIe connector comprises a PCIe x16 connector and the second PCIe connector comprises a PCIe x8 connector.

19. A circuit board, comprising:

a first peripheral component interconnect express (PCIe) connector configured to be inserted into a first connector of a second circuit board, wherein the first PCIe connector extends from a side of the circuit board a first length, wherein the first PCIe connector comprises a PCIe x16 connector; and

a second PCIe connector configured to be inserted into to a second connector of the second circuit board, wherein the second PCIe connector extends from the side of the circuit board a second length that is less than the first length, wherein the first PCIe connector and the second PCIe connector extend from the same side of the circuit board, wherein the first PCIe connector and the second PCIe connector extend from the side of the circuit board in parallel, wherein the first PCIe connector is offset from the second PCIe connector in a first direction and a second direction, wherein the first direction and the second direction are perpendicular to each other, and wherein the second PCIe connector comprises a PCIe x8 connector.

20. The circuit board of claim 19 , wherein the circuit board is a device under test (DUT) board configured to receive a programmable logic device as a device under test.