EMBEDDED MULTI-DIE INTERCONNECT BRIDGE WITH IMPROVED POWER DELIVERY
Integrated circuit packages with multiple integrated circuit dies are provided. A multichip package may include at least two integrated circuit dies that communicate using an embedded multi-die interconnect bridge (EMIB) in a substrate of the multi-chip package. The EMIB may receive power at contact pads formed at a back side of the EMIB that are coupled to a back side conductor on which the EMIB is mounted. The back side conductor may be separated into multiple regions that are electrically isolated from one another and that each receive a different power supply voltage signal or data signal from a printed circuit board. These power supply voltage signals and data signals may be provided to the two integrated circuit dies through internal microvias or through-silicon vias formed in the EMIB.
1 . A multi-chip package, comprising:
an interconnect bridge having a first contact pad and a second contact pad thereon, the interconnect bridge comprising a silicon die;
a conductive structure laterally adjacent the interconnect bridge;
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure;
a second dielectric layer on the first dielectric layer, the second dielectric layer over the interconnect bridge and over the conductive structure;
a first via in the second dielectric layer, the first via coupled to the first contact pad;
a second via in the second dielectric layer, the second via coupled to the second contact pad;
a third via in the second dielectric layer, the third via coupled to the conductive structure;
a third dielectric layer on the second dielectric layer, the third dielectric layer over the interconnect bridge and over the conductive structure;
a first die over the third dielectric layer, the first die over the interconnect bridge and over the conductive structure; and
a second die over the interconnect bridge, the second die coupled to the first die by the interconnect bridge.
2 . The multi-chip package of claim 1 , further comprising:
one or more through silicon vias in the silicon die.
3 . The multi-chip package of claim 1 , wherein the conductive structure has a vertical length greater than a vertical length of each of the first via and the second via.
4 . The multi-chip package of claim 1 , wherein the conductive structure has a vertical length greater than a vertical length of each of the first contact pad and the second contact pad.
5 . The multi-chip package of claim 1 , further comprising:
a cavity laterally between the interconnect bridge and the first dielectric layer.
6 . The multi-chip package of claim 1 , wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
7 . The multi-chip package of claim 1 , wherein the first die is a main die, and the second die is a secondary die.
8 . The multi-chip package of claim 7 , wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
9 . The multi-chip package of claim 1 , wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch.
10 . The multi-chip package of claim 9 , wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.
11 . A multi-chip package, comprising:
an interconnect bridge having a first contact pad and a second contact pad thereon, the interconnect bridge having one or more through vias;
a conductive structure laterally adjacent the interconnect bridge;
a first dielectric layer, the first dielectric layer laterally adjacent the interconnect bridge, and the first dielectric layer laterally adjacent and in contact with the conductive structure;
a second dielectric layer on the first dielectric layer, the second dielectric layer over the interconnect bridge and over the conductive structure;
a first via in the second dielectric layer, the first via coupled to the first contact pad;
a second via in the second dielectric layer, the second via coupled to the second contact pad;
a third via in the second dielectric layer, the third via coupled to the conductive structure;
a third dielectric layer on the second dielectric layer, the third dielectric layer over the interconnect bridge and over the conductive structure;
a first die over the third dielectric layer, the first die over the interconnect bridge and over the conductive structure; and
a second die over the interconnect bridge, the second die coupled to the first die by the interconnect bridge.
12 . The multi-chip package of claim 11 , further comprising:
a conductive via vertically beneath the interconnect bridge.
13 . The multi-chip package of claim 11 , wherein the conductive structure has a vertical length greater than a vertical length of each of the first via and the second via.
14 . The multi-chip package of claim 11 , wherein the conductive structure has a vertical length greater than a vertical length of the first contact pad and the second contact pad.
15 . The multi-chip package of claim 11 , further comprising:
a cavity laterally between the interconnect bridge and the first dielectric layer.
16 . The multi-chip package of claim 11 , wherein the interconnect bridge is laterally spaced apart from the first dielectric layer.
17 . The multi-chip package of claim 11 , wherein the first die is a main die, and the second die is a secondary die.
18 . The multi-chip package of claim 17 , wherein the main die is a die selected from the group consisting of a central processing unit (CPU) die, a graphics processing unit (GPU) die, and an application-specific integrated circuit (ASIC) die, and wherein the secondary die is a die selected from the group consisting of a memory die and a transceiver die.
19 . The multi-chip package of claim 11 , wherein the first die is coupled to the interconnect bridge by a first plurality of conductive bumps having a first pitch, and wherein the first die further comprises a second plurality of conductive bumps having a second pitch greater than the first pitch.
20 . The multi-chip package of claim 19 , wherein the second die is coupled to the interconnect bridge by a third plurality of conductive bumps having a third pitch, and wherein the second die further comprises a fourth plurality of conductive bumps having a fourth pitch greater than the third pitch.