Integrated Circuit Device with Separate Die for Programmable Fabric and Programmable Fabric Support Circuitry
An integrated circuit device having separate dies for programmable logic fabric and circuitry to operate the programmable logic fabric are provided. A first integrated circuit die may include field programmable gate array fabric. A second integrated circuit die may be coupled to the first integrated circuit die. The second integrated circuit die may include fabric support circuitry that operates the field programmable gate array fabric of the first integrated circuit die.
1 . A data processing system comprising:
a processor configured to manage a data processing request; and
a programmable logic device configured to be programmed with a configuration program relating to the data processing request in response to an instruction by the processor, wherein programmable logic fabric of a first integrated circuit die of the programmable logic device is programmed at least in part by fabric support circuitry of a second integrated circuit die of the programmable logic device.
2 . The data processing system of claim 1 , wherein the fabric support circuitry of the second integrated circuit die of the programmable logic device comprises a device controller configured to control circuitry of the first integrated circuit die and the second integrated circuit die, a sector controller configured to control a sector of circuitry of the first integrated circuit die and the second integrated circuit die, a network on chip, a configuration network on chip, data routing circuitry, sector-aligned memory, a memory controller configured to program the programmable logic fabric, an input/output (I/O) interface for the programmable logic fabric, an external memory interface, a first processor embedded in the second integrated circuit die, an interface to connect the programmable logic fabric to a second processor external to the first integrated circuit die and the second integrated circuit die, voltage control circuitry configured to control a voltage supplied to the programmable logic fabric, thermal monitoring circuitry configured to monitor heat of the first integrated circuit die, a decoupling capacitor, a power clamp, electrostatic discharge circuitry, or any combination thereof.
3 . The data processing system of claim 1 , wherein the processor and the programmable logic device are disposed within the same package.
4 . The data processing system of claim 1 , wherein the data processing request comprises machine learning, video processing, voice recognition, image recognition, data compression, database search ranking, bioinformatics, network security pattern identification, spatial navigation, or a combination thereof.
5 . The data processing system of claim 1 , wherein the programmable logic device comprises a field programmable gate array (FPGA).
6 . A method for manufacturing an integrated circuit device, the method comprising:
obtaining a first integrated circuit die comprising field programmable gate array fabric;
obtaining a second integrated circuit die comprising fabric support circuitry configured to operate the field programmable gate array fabric of the first integrated circuit die;
vertically aligning the first integrated circuit die and the second integrated circuit die; and
connecting a first surface of the first integrated circuit die to a second surface of the second integrated circuit die.
7 . The method of claim 6 , wherein obtaining the first integrated circuit die comprises manufacturing the first integrated circuit die according to a higher-resolution process, and wherein obtaining the second integrated circuit die comprises manufacturing the second integrated circuit die according to a lower-resolution process.
8 . The method of claim 6 , comprising disposing the first integrated circuit die and the second integrated circuit die in a microchannel integrated heat spreader.
9 . The method of claim 6 , wherein vertically aligning the first integrated circuit die and the second integrated circuit die comprises vertically aligning first sectors of the field programmable gate array fabric with second sectors of the fabric support circuitry.
10 . The method of claim 6 , wherein connecting the first surface and the second surface comprises forming an electrical connection between a connector of the first integrated circuit die and a corresponding connector of the second integrated circuit die.
11 . The method of claim 10 , wherein the electrical connection comprises a microbump.
12 . The method of claim 6 , wherein the integrated circuit device comprises a field programmable gate array (FPGA) comprising the first integrated circuit die and the second integrated circuit die.
13 . The method of claim 6 , comprising electrically coupling a processor to the second integrated circuit die, the processor configured to manage a data processing request for the first integrated circuit die and the second integrated circuit die.
14 . The method of claim 6 , wherein the second integrated circuit die comprises sector-aligned memory corresponding to one or more fabric sectors of the field programmable gate array fabric, wherein the sector-aligned memory is configured to store configuration data for programming the one or more fabric sectors.
15 . A method of manufacturing a field programmable gate array (FPGA) comprising:
obtaining a first integrated circuit die comprising field programmable gate array fabric;
obtaining a second integrated circuit die comprising fabric support circuitry configured to operate the field programmable gate array fabric of the first integrated circuit die; and
electrically coupling the first integrated circuit die and the second integrated circuit die such that the fabric support circuitry is communicatively coupled to the field programmable gate array fabric.
16 . The method of claim 15 , comprising aligning one or more sectors of the field programmable gate array fabric with one or more corresponding sectors of the fabric support circuitry.
17 . The method of claim 16 , wherein the fabric support circuitry is configured to:
receive configuration data indicative of programming for the field programmable gate array fabric;
store the configuration data in the one or more corresponding sectors of the fabric support circuitry; and
program the one or more sectors of the field programmable gate array fabric according to the programming.
18 . The method of claim 17 , comprising physically coupling the first integrated circuit die and the second integrated circuit die within a single package.
19 . The method of claim 18 , wherein physically coupling the first integrated circuit die and the second integrated circuit die within the single package comprises physically coupling the first integrated circuit die and the second integrated circuit die to a microchannel heat spreader within the single package.
20 . The method of claim 18 , wherein electrically coupling the first integrated circuit die and the second integrated circuit die comprises communicatively coupling the fabric support circuitry and the field programmable gate array fabric via one or more silicon bridges, one or more interposers, through-silicon via (TSVs) or any combination thereof.