Granted Patent B2

US 8,136,020 · App. 11/987,300 · Granted Mar 13, 2012

Abstract

Claims (61)

1. An apparatus for performing forward error correction comprising:

a first encoder operable to:

encode input data using a first error correcting code, and

arrange said encoded data into an outer frame, wherein the outer frame is a frame of parallel data blocks, and wherein the outer frame comprises appended redundancy bits corresponding to the first error correcting code;

an interleaver operable to interleave the outer frame to generate an intermediate frame comprising serial data blocks; and

a second encoder operable to append redundancy bits corresponding to a second error correcting code to the intermediate frame to generate an inner frame.

2. The apparatus of claim 1 further comprising:

a first decoder operable to:

correct errors in the inner frame by utilizing the redundancy bits of the second error correcting code, and

remove the redundancy bits of the second error correcting code to generate a reconstructed intermediate frame;

a de-interleaver operable to de-interleave the reconstructed intermediate frame to generate a reconstructed outer frame; and

a second decoder operable to correct errors in the reconstructed outer frame by utilizing the redundancy bits of the first error correcting code and generate a decoded outer frame.

3. The apparatus of claim 2 , wherein a second encoding using the second error correcting code is performed.

4. The apparatus of claim 2 further comprising circuitry operable to:

interleave the decoded outer frame;

generate a decoded inner frame by appending redundancy bits of the second error correcting code to the decoded outer frame;

detect errors in the decoded inner frame using the redundancy bits of the second error correcting code;

correct the detected errors to generate corrected data; and

output the corrected data.

5. The apparatus of claim 1 , wherein the first error correcting code is an outer code that is shortened from a parent error correcting code.

6. The apparatus of claim 5 , wherein the interleaver is further operable to perform the interleaving using orthogonal mapping for higher coding gain.

7. The apparatus of claim 1 , wherein the first error correcting code is a Bose-Ray-Chaudhuri-Hocquenghem (BCH) BCH( 3896 , 3824 ) code.

8. The apparatus of claim 1 , wherein the second error correcting code is a BCH( 2040 , 1952 ) code shortened from a BCH( 2047 , 1959 ) parent error correcting code.

9. The apparatus of claim 1 , wherein the first encoder encodes the input data by mapping the input data into a plurality of groups and encoding each group using the first error correcting code.

10. A method for forward error correction, the method comprising:

encoding, using a first encoder, input data using a first error correcting code;

arranging, using the first encoder, said encoded data into an outer frame, wherein the outer frame is a frame of parallel data blocks, and wherein the outer frame comprises appended redundancy bits corresponding to the first error correcting code;

interleaving, using an interleaver, the outer frame to generate an intermediate frame comprising serial data blocks; and

appending, using a second encoder, redundancy bits corresponding to a second error correcting code to the intermediate frame to generate an inner frame.

11. The method of claim 10 further comprising:

correcting errors, using a first decoder, in the inner frame by utilizing the redundancy bits of the second error correcting code;

removing, using the first decoder, the redundancy bits of the second error correcting code to generate a reconstructed intermediate frame;

de-interleaving, using a de-interleaver, the reconstructed intermediate frame to generate a reconstructed outer frame; and

correcting errors in the reconstructed outer frame, using a second decoder, by utilizing the redundancy bits of the first error correcting code to generate a decoded outer frame.

12. The method of claim 11 , wherein a second encoding using the second error correcting code is performed.

13. The method of claim 11 further comprising:

interleaving, using circuitry, the decoded outer frame;

generating, using the circuitry, a decoded inner frame by appending redundancy bits of the second error correcting code to the decoded outer frame;

detecting, using the circuitry, errors in the decoded inner frame using the redundancy bits of the second error correcting code;

correcting, using the circuitry, the detected errors to generate corrected data; and

outputting, using the circuitry, the corrected data.

14. The method of claim 10 , wherein the first error correcting code is an outer code that is shortened from a parent error correcting code.

15. The method of claim 14 , wherein the interleaver is further operable to perform the interleaving using orthogonal mapping for higher coding gain.

16. The method of claim 10 , wherein the first error correcting code is a Bose-Ray-Chaudhuri-Hocquenghem (BCH) BCH( 3896 , 3824 ) code.

17. The method of claim 10 , wherein the second error correcting code is a BCH( 2040 , 1952 ) code shortened from a BCH( 2047 , 1959 ) parent error correcting code.

18. The method of claim 10 , wherein the first encoder encodes the input data by mapping the input data into a plurality of groups and encoding each group using the first error correcting code.

19. A method for forward error correction, the method comprising:

encoding, using a first encoder, input data using a first error correcting code;

arranging, using the first encoder, said encoded data into an outer frame, wherein the outer frame is a frame of parallel data blocks, and wherein the outer frame comprises appended redundancy bits corresponding to the first error correcting code;

interleaving, using an interleaver, the outer frame to generate an intermediate frame comprising serial data blocks;

appending, using a second encoder, redundancy bits corresponding to a second error correcting code to the intermediate frame to generate an inner frame;

correcting, using decoding circuitry, errors in the inner frame by utilizing the redundancy bits of the second error correcting code;

removing, using the decoding circuitry, the redundancy bits of the second error correcting code to generate a reconstructed intermediate frame;

de-interleaving the reconstructed intermediate frame, using the decoding circuitry, to generate a reconstructed outer frame; and

correcting errors in the reconstructed outer frame, using the decoding circuitry, by utilizing the redundancy bits of the first error correcting code to generate a decoded outer frame.

20. The method of claim 19 further comprising:

interleaving the decoded outer frame;

generating a decoded inner frame by appending redundancy bits of the second error correcting code;

detecting errors in the decoded inner frame using the redundancy bits of the second error correcting code;

correcting the detected errors to generate corrected data; and

outputting corrected data.

Assignments (11)