At-speed burst sampling for user registers
Systems and methods described herein may relate to burst sampling of an integrated circuit device. Such a system may include a first logic access block including a data register and a second logic access block including a memory column. The memory column may be configurable to operate as a First In, First Out (FIFO), user lookup table (LUT) mode, or as user random access memory (RAM). The memory column may store data sampled from the data register for any number of clock cycles and the data may be sampled at the speed of a clock of a device under test (DUT).
1. An integrated circuit, comprising:
a first logic block, the first logic block comprising a data register configurable to store data; and
a second logic block, the second logic block comprising a memory column coupled to the data register, wherein the memory column is configurable to operate as a First In, First Out (FIFO) to sample data from the data register for a plurality of clock cycles and at a speed of a clock of the integrated circuit.
2. The integrated circuit of claim 1 , comprising an interconnect region disposed between the first logic block and the second logic block.
3. The integrated circuit of claim 2 , wherein the interconnect region is configurable to couple the data register to the memory column.
4. The integrated circuit of claim 2 , wherein the interconnect region comprises a multiplexer configured to couple the data register to the memory column.
5. The integrated circuit of claim 1 , wherein the second logic block comprises a second memory column, wherein the second memory column is configurable to operate as a second FIFO to sample data from the data register for the plurality of clock cycles and at the speed of the clock.
6. The integrated circuit of claim 1 , wherein the first logic block comprises a second data register coupled to the memory column, wherein the memory column is configurable to operate as the FIFO to sample data from the data register and the second data register for the plurality of clock cycles.
7. The integrated circuit of claim 1 , comprising:
the first logic block comprising a second data register; and
the second logic block comprising a second memory column coupled to the second data register, wherein the second memory column is configurable to operate as a second FIFO to sample data from the second data register for the plurality of clock cycles.
8. The integrated circuit of claim 7 , wherein the second memory column is configurable to operate as user lookup table (LUT) mode or user random access memory (RAM) when not configured as the second FIFO.
9. The integrated circuit of claim 1 , wherein the memory column comprises at least thirty-two memory cells.
10. The integrated circuit of claim 9 , wherein the memory column is configurable to store data from the data register in at least sixteen memory cells.
11. The integrated circuit of claim 10 , wherein the data from the data register is from at least sixteen continuous clock cycles.
12. The integrated circuit of claim 9 , wherein the second logic block comprises a second memory column, wherein the second memory column comprises at least thirty-two memory cells.
13. The integrated circuit of claim 12 , wherein the memory column and the second memory column are configurable to store data from the data register from at least sixty-four continuous clock cycles.
14. The integrated circuit of claim 9 , wherein the memory column is configurable to store data from the data register from thirty-two continuous clock cycles.
15. A system comprising:
programmable logic circuitry comprising a plurality of configuration memory, the programmable logic circuitry comprising:
a first logic block comprising a first data register and a second data register; and
a second logic block comprising a first memory column, wherein the first memory column is coupled to the first data register and the second data register, and wherein the first memory column is configurable to sample data from the first data register and the second data register for a plurality of clock cycles.
16. The system of claim 15 , wherein the programmable logic circuitry comprises:
a first multiplexer configured to couple the first data register and the first memory column; and
a second multiplexer configured to couple the second data register and the first memory column.
17. The system of claim 15 , wherein the second logic block comprises a second memory column, wherein the second memory column is coupled to the first data register and the second data register.
18. The system of claim 17 , wherein the second memory column is configurable to sample data from the first data register and the second data register for the plurality of clock cycles.
19. The system of claim 17 , wherein the plurality of clock cycles comprises at least sixteen clock cycles.
20. A method comprising:
sampling first data from a first register of programmable logic circuitry, the first data sampled for a plurality of clock cycles at a clock speed of the programmable logic circuitry; and
storing the first data at a memory column of the programmable logic circuitry, wherein the memory column is configurable to operate as a First In, First Out (FIFO) in a first mode, configurable to operate as user lookup table (LUT) in a second mode, and configurable to operate as user random access memory (RAM) in a third mode.