Universal transceiver container
The present disclosure relates to modular transceiver-based network circuitries that may include internal configurable interfaces or gaskets. The configurable gaskets may facilitate integration of the network circuitries in electronic devices by providing a transparent interface to processing circuitries coupled to the network circuitries. Moreover, the configurable gaskets may also have a floorplan layout (e.g., a chiplet layout) that may facilitate coupling of multiple network circuitries to a single processing circuitry, in a modular manner.
1. A network adaptor, comprising:
a plurality of physical coding sublayer (PCS) lanes;
a protocol intellectual property (IP) block configured to implement a first protocol;
a physical medium attachment (PMA) gasket circuitry configured to couple the PCS lanes to the protocol IP block;
an interconnect bus interface configured to provide connectivity between the network adaptor to an interconnect bus; and
a digital gasket circuitry configured to couple the protocol IP block to the interconnect bus interface.
2. The network adaptor of claim 1 , wherein the first protocol comprises a peripheral component interconnect express (PCIe) protocol, an Ethernet protocol, an Interlaken protocol, a serial advance technology attachment (SATA) protocol, an optical transport network (OTN) protocol, an UltraPath Interconnect (UPI) protocol, or a Common Public Radio Interface Protocol (CPRI), or any combination thereof.
3. The network adaptor of claim 1 , wherein the protocol IP block implements a non-return-to-zero (NRZ) encoding, and wherein the digital gasket circuitry is configured to provide a 1-to-1 mapping for transmission and/or reception of serial data.
4. The network adaptor of claim 1 , wherein the protocol IP block implements a 4-level pulse-amplitude modulation (PAM4) encoding, and wherein the digital gasket circuitry is configured to provide a 2-to-1 mapping for transmission of serial data from the protocol IP block to the PCS lanes and a 1-to-2 mapping for reception of serial data from the PCS lanes to the protocol IP block.
5. The network adaptor of claim 1 , wherein interconnect bus interface comprises an application-specific integrated circuit (ASIC) interconnect bus (AIB).
6. The network adaptor of claim 1 , wherein the protocol IP block comprises hardened digital circuitry, and wherein the PMA gasket circuitry and the digital gasket circuitry comprises programmable fabric.
7. The network adaptor of claim 1 , comprising:
a high-speed serial interface (HSSI) circuitry configured to exchange control and status signals from the interconnect bus interface;
a digital control gasket circuitry configured to couple the HSSI circuitry to the protocol IP block; and
an analog control gasket circuitry configured to couple the HSSI circuitry to the PCS lanes.
8. The network adaptor of claim 7 , wherein the HSSI circuitry comprises hardened circuitry, and wherein the digital gasket circuitry and the analog gasket circuitry comprises programmable fabric.
9. The network adaptor of claim 1 , comprising a configurable clock network configured to provide a plurality of clock signals to the PCS lanes.
10. The network adaptor of claim 1 , wherein the network adaptor comprises a chiplet network adaptor.
11. The network adaptor of claim 1 , comprising:
a second plurality of PCS lanes;
a second protocol IP block configured to implement a second protocol; and
a second PMA gasket circuitry configured to couple the second plurality of PCS lanes to the second protocol IP block.
12. The network adaptor of claim 11 , wherein the second protocol is the same as the first protocol or the second protocol is different from the first protocol.
13. An electronic device comprising:
processing circuitry comprising an interconnect bus interface; and
network circuitry coupled to the processing circuitry via the interconnect bus interface, wherein the network circuitry comprises:
a first plurality of physical coding sublayer (PCS) lanes;
a first protocol intellectual property (IP) block configured to implement a protocol;
a first physical medium attachment (PMA) gasket circuitry configured to couple the first plurality of PCS lanes to the first protocol IP block;
an interconnect bus interface configured to provide connectivity between the network circuitry to an interconnect bus;
a digital gasket circuitry configured to couple the first protocol IP block to the interconnect bus interface;
a high-speed serial interface (HSSI) circuitry configured to exchange control and status signals from the interconnect bus interface;
a digital control gasket circuitry configured to couple the HSSI circuitry to the first protocol IP block; and
an analog control gasket circuitry configured to couple the HSSI circuitry to the PCS lanes.
14. The electronic device of claim 13 , wherein the processing circuitry comprises a high-speed serial controller configured to send and receive the control and status signals to the HSSI circuitry of the network circuitry.
15. The electronic device of claim 13 , wherein the interconnect bus interface is configured to couple to an application-specific integrated circuit (ASIC) interconnect bus (AIB).
16. The electronic device of claim 13 , wherein the processing circuitry comprises a second interconnect bus interface that comprises a universal interconnect bus (UIB) interface.
17. The electronic device of claim 16 , comprising a high-bandwidth memory (HMB) device coupled to the processing circuitry using the UIB interface.
18. The electronic device of claim 13 , wherein the network circuitry comprises a first network chiplet.
19. The electronic device of claim 18 , wherein the processing circuitry is configured to couple to a second network chiplet.
20. The electronic device of claim 19 , wherein the first network chiplet comprises an Ethernet chiplet and the second network chiplet comprises a peripheral component interconnect express (PCIe) chiplet.
21. The electronic device of claim 13 , comprising a second protocol IP block configured to implement a second protocol, wherein the second protocol IP block is configured to couple to a second plurality of PCS lanes via a second PMA gasket.
22. A method to configure a network interface comprising a plurality of transceivers, a protocol intellectual property (IP) block, a physical medium attachment (PMA) gasket, and a digital gasket, the method comprising:
receiving a protocol specification for an interconnect bus;
configuring the digital gasket that couples the protocol IP block to the interconnect bus based on the received protocol specification and a protocol of the protocol IP block;
determining a PMA coding based on the received protocol specification; and
configuring the PMA gasket based on the PMA coding, wherein configuring the PMA gasket comprises mapping at least one physical coding sublayer (PCS) lane of a plurality of PCS lanes to a logical lane of the protocol IP block.
23. The method of claim 22 , comprising:
determining a data rate associated with the received protocol specification; and
configuring a clock network of the network interface to provide clocking signals to the plurality of PCS lanes.
24. The method of claim 22 , comprising:
configuring a digital control gasket that couples a high-speed serial interface (HSSI) circuitry of the network interface to the protocol IP block based on the received protocol specification and the protocol of the protocol IP block; and
configuring an analog control gasket that couples the HSSI circuitry to the plurality of PCS lanes.