Efficient logic blocks architectures for dense mapping of multipliers

1. An integrated circuit, comprising a logic block configurable to perform multiplication operations, wherein the logic block comprises:

a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs;

a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:

receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal; and

provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal;

adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs; and

circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.

2. The integrated circuit of claim 1 , further comprising a first adder configurable to determine a sum of a first portion of the second plurality of outputs and a first portion of the third plurality of outputs.

3. The integrated circuit of claim 2 , further comprising additional circuitry configurable to:

receive the portion of the plurality of inputs and the sum; and

determine a second sum of the portion of the plurality of inputs and the sum.

4. The integrated circuit of claim 3 , wherein the logic block is configurable to generate eight partial products.

5. The integrated circuit of claim 3 , wherein:

the adding circuitry is configurable to receive a first carry-in value from a second logic block;

the circuitry is configurable to generate a second carry-in value from the second logic block; and

the additional circuitry is configurable to generate a third carry-in value from the second logic block.

6. The integrated circuit of claim 1 , wherein the logic block is configurable to perform signed and unsigned multiplication operations.

7. The integrated circuit of claim 1 , wherein the first portion of the plurality of lookup tables and the second portion of the plurality of lookup tables are configurable to receive a third bit value, and a fourth bit value of the plurality of inputs.

8. The integrated circuit of claim 1 , wherein the integrated circuit comprises a programmable logic device.

9. The integrated circuit of claim 8 , wherein the programmable logic device comprises a field-programmable gate array (FPGA).

10. The integrated circuit of claim 1 , wherein the first plurality of outputs comprises four partial products generated based on the plurality of inputs.

11. The integrated circuit of claim 10 , wherein the third plurality of outputs comprises two partial products.

12. The integrated circuit of claim 11 , further comprising:

a first adder configurable to determine a first sum of a first portion of the second plurality of outputs and a first partial product of the two partial products; and

a second adder configurable to determine a second sum of a second portion of the second plurality of outputs and a second partial product of the two partial products.

13. A logic block implementable on a programmable logic device, the logic block comprising:

a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs;

a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:

receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal; and

provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal;

adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs; and

circuitry configurable to receive a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.

14. The logic block of claim 13 , wherein:

the plurality of inputs comprises a first input and second input, wherein the first input and the second input each comprise up to four bits; and

the logic block is configured to generate six partial products.

15. The logic block of claim 13 , wherein the logic block further comprises an adder configured to receive a portion of the second plurality of outputs, a carry-in value from a second logic block communicatively coupled to the logic block, and a portion of the third plurality of outputs.

16. The logic block of claim 13 , wherein:

the first portion of the plurality of lookup tables is configurable to receive a third bit value, a fourth bit value, and a fifth bit value of the plurality of inputs;

the second portion of the plurality of lookup tables is configurable to receive the third bit value, the fourth bit value, and a sixth bit value of the plurality of inputs; and

the circuitry is configurable to receive the second bit value or the fifth bit value of the plurality of inputs.

17. An integrated circuit device, comprising a plurality of logic blocks, wherein each logic block of the plurality of logic blocks comprises:

a plurality of lookup tables configurable to receive a plurality of inputs and generate a first plurality of outputs, wherein a first portion of the plurality of lookup tables is configurable to receive a first bit value of the plurality of inputs;

a multiplexer communicatively coupled to a second portion of the plurality of lookup tables that is different than the first portion of the plurality of lookup tables, wherein the multiplexer is configurable to:

receive the first bit value of the plurality of inputs, a second bit value of the plurality of inputs, and a control signal; and

provide either the first bit value or the second bit value to the second portion of the plurality of lookup tables based on the control signal;

adding circuitry configurable to receive the first plurality of outputs and generate a second plurality of outputs; and

circuitry configurable to receive at least a portion of the plurality of inputs, determine one or more partial products, and generate a third plurality of outputs.

18. The integrated circuit device of claim 17 , wherein the circuitry is configurable to receive an enable/disable signal to disable the circuitry when the circuitry is not used.

19. The integrated circuit device of claim 17 , wherein the plurality of logic blocks comprises a first logic block and a second logic block communicatively coupled to the first logic block, wherein:

the first logic block is configurable to generate two non-carry bits, a first carry bit, and a second carry bit; and

the adding circuitry of the second logic block is configurable to receive the first carry bit.

20. The integrated circuit device of claim 19 , wherein the second logic block comprises an adder configurable to receive the second carry bit.