Coarse-grain programmable routing network for logic devices
Circuitry is provided that includes programmable fabric with fine-grain routing wires and a separate programmable coarse-grain routing network that provides enhanced bandwidth, low latency, and deterministic routing behavior. The programmable coarse-grain routing network may be implemented on an active interposer die. The programmable fabric may be implemented on a top die that is stacked on the active interposer die. A protocol-based network on chip (NoC) may be overlaid on the coarse-grain routing network. Although the NoC protocol is nondeterministic, the coarse-grain routing network includes an array of programmable switch boxes linked together using a predetermined number of routing channels to provide deterministic routing. Pipeline registers may be interposed within the routing channels at fixed locations to guarantee timing closure.
1. Circuitry, comprising:
a first die that includes fine-grain routing wires, wherein the fine-grain routing wires have variable routing lengths; and
a second die that includes a coarse-grain routing network, wherein the coarse-grain routing network includes a plurality of channels forming a deterministic routing path with guaranteed timing closure, and wherein global routing for the first die is performed using the coarse-grain routing network on the second die.
2. The circuitry of claim 1 , wherein the coarse-grain routing network comprises pipeline registers at fixed locations on the second die.
3. The circuitry of claim 2 , wherein register pipelining on the first die is not fixed.
4. The circuitry of claim 1 , wherein the fine-grain routing wires have bit-level granularity.
5. The circuitry of claim 4 , wherein the coarse-grain routing network has byte-level granularity.
6. The circuitry of claim 1 , wherein multi-bit buses in the fine-grain routing wires take different routing paths on the first die.
7. The circuitry of claim 6 , wherein multi-bit buses in the coarse-grain routing network take the same routing path on the second die.
8. The circuitry of claim 1 , wherein the coarse-grain routing network is configured to implement a protocol-based network on chip, and wherein the protocol-based network on chip is nondeterministic.
9. The circuitry of claim 1 , wherein the first die is stacked on the second die.
10. The circuitry of claim 1 , wherein only the first die includes configuration random-access memory.
11. The circuitry of claim 1 , wherein the first die includes memory blocks of a first size and density, and wherein the second die includes memory blocks of a second size and density that is greater than the first size and density.
12. The circuitry of claim 1 , wherein the coarse-grain routing network comprises an array of switch box circuits interconnected via the plurality of channels.
13. The circuitry of claim 12 , wherein each switch box circuit in the array of switch box circuits comprises a plurality of switch boxes, and wherein a switch box in the plurality of switch boxes comprises:
a data path routing multiplexer having a first input coupled to an interconnect from a first direction, a second input coupled to an interconnect from a second direction perpendicular to the first direction, a third input coupled to an interconnect from a third direction perpendicular to the first and second directions, and a fourth input configured to receive a signal from the first die.
14. The circuitry of claim 13 , wherein the switch box further comprises:
a selection multiplexer having a first input configured to receive a static control bit from a configuration random-access memory cell on the first die, a second input configured to receive a control signal from the first die, and a third signal coupled to a time-domain multiplexing counter.
15. The circuitry of claim 13 , wherein the switch box further comprises:
an additional multiplexer having a first input configured to receive signals from the data path routing multiplexer and a second input coupled to a network on chip (NoC) bridge component on the first die.
16. Apparatus, comprising:
programmable fabric that includes logic circuitry, digital signal processing (DSP) blocks, random-access memory (RAM) blocks, and fine-grain routing wires; and
a coarse-grain routing network coupled to the programmable fabric, wherein the coarse-grain routing network provides a deterministic routing path formed using a plurality of channels timing closed to a specified data transfer rate.
17. The apparatus of claim 16 , wherein the fine-grain routing wires cannot guarantee the specified data transfer rate.
18. The apparatus of claim 16 , wherein the coarse-grain routing network comprises a grid of switch boxes forming a plurality of grid slots, and wherein at least some of the plurality of grid slots are occupied by additional memory blocks, additional compute blocks, or input-output blocks.
19. Programmable circuitry, comprising:
fine-grain routing wires configured to provide a first level of routing granularity; and
a coarse-grain routing network configured to provide a second level of routing granularity that is different than the first level of routing granularity, wherein the coarse-grain routing network is operable in a first mode during which channels in the coarse-grain routing network are configured using a fixed bandwidth allocation and is further operable in a second mode during which the channels in the coarse-grain routing network are configured using a dynamically-scheduled bandwidth allocation.
20. The programmable circuitry of claim 19 , further comprising logic circuitry, wherein the coarse-grain routing network is further operable in a third mode during which the channels in the coarse-grain routing network are configured at run-time using control signals generated by the logic circuitry.