High-speed core interconnect for multi-die programmable logic devices
Systems and methods related to multi-die integrated circuits that may include dies having high-speed core interconnects. The high-speed core interconnects may be used to directly connect two adjacent dies.
1. A programmable logic device comprising:
a first die;
a second die; and
a third die coupled to the first die through a first interface and coupled to the second die through a second interface, wherein the first interface, the second interface, or both comprise a microbump interface, wherein the third die is coupled to a plurality of interconnect layers, wherein the plurality of interconnect layers comprise one or more hardened data buses used to create one or more routes between different regions of a programmable fabric layer of the third die.
2. The programmable logic device of claim 1 , wherein at least one interconnect layer of the plurality of interconnect layers comprises the first interface, the second interface, and a core interconnect.
3. The programmable logic device of claim 1 , wherein the first interface is configured to be coupled to the second interface via a core interconnect.
4. The programmable logic device of claim 3 , wherein the core interconnect comprises a plurality of repeaters.
5. The programmable logic device of claim 4 , wherein the plurality of repeaters comprise a separation in a range between 350 microns and 400 microns.
6. The programmable logic device of claim 1 , wherein the first interface, the second interface, and a core interface between the first interface and the second interface are used for one or more data transfers between the first die and the second die.
7. The programmable logic device of claim 6 , wherein the one or more data transfers are routed between the first die and the second die by traversing the third die.
8. The programmable logic device of claim 6 , wherein the one or more data transfers are routed between the first die and the second die without traversing the third die.
9. The programmable logic device of claim 1 , wherein the first die, second die, or both comprise programmable logic.
10. The programmable logic device of claim 1 , wherein the third die comprises an input/output die that comprises transceiver circuitry.
11. A system, comprising:
a host processor; and
a programmable logic device communicatively coupled to the host processor, the programmable logic device comprising:
a first die coupled to a programmable die via a first interface; and
a second die coupled to the programmable die via a second interface, wherein the first interface, second interface, or both comprise a plurality of microbump bridges, wherein the programmable die is coupled to a plurality of interconnect layers, wherein the plurality of interconnect layers comprise one or more hardened data buses configured to dynamically reconfigure one or more routes in a programmable fabric layer of the programmable die.
12. The system of claim 11 , wherein the host processor is configured to assign priority to a data transfer between the first die and the second die based on determining that the data transfer traverses the programmable die.
13. The system of claim 11 , wherein the host processor is configured to assign priority to a data transfer between the first die and the second die based on determining that the data transfer does not traverse the programmable die.
14. The system of claim 11 , wherein at least one interconnect layer of the plurality of interconnect layers comprises the first interface, the second interface, and a core interconnect.
15. The system of claim 11 , wherein the first interface is configured to be coupled to the second interface via a core interconnect.
16. The system of claim 15 , wherein the core interconnect comprises a plurality of repeaters.
17. A method, comprising:
determining a data transfer between a first die of a programmable logic device and a second die of the programmable logic device through a third die of the programmable logic device, wherein the third die is coupled to the first die through a first interface and coupled to the second die through a second interface, wherein the third die comprises a core interconnect that couples the first interface and the second interface, wherein the core interconnect comprises a plurality of repeaters, and wherein the third die comprises a hardened data bus used to create a route between different regions of a programmable fabric layer of the third die;
assigning a portion of the core interconnect of the third die to the data transfer;
generating a bitstream comprising the portion of the core interconnect of the third die assigned to the data transfer; and
configuring the programmable logic device using the bitstream.
18. The method of claim 17 , wherein the first interface, the second interface, or both comprise a microbump interface.
19. The method of claim 17 , comprising assigning priority to one or more data transfers between the first die and the second die in response to a number of the one or more data transfers exceeding available number of data channels in the third die.
20. The method of claim 17 , wherein the third die comprises an input/output die that comprises transceiver circuitry.