SINGLE INSTRUCTION, MULTIPLE THREAD (SIMT) PROCESSORS, METHODS, SYSTEMS, AND INSTRUCTIONS
A processor of an aspect includes an instruction unit to receive a single instruction, multiple thread (SIMT) instruction. The SIMT instruction has at least one field to provide at least one value. The at least one value is to indicate a plurality of threads that are to execute the SIMT instruction. The processor also includes a SIMT processor coupled with the instruction unit. The SIMT processor is to execute the SIMT instruction for each of the plurality of threads. Other processors, methods, systems, and machine-readable medium storing such a SIMT instructions are also disclosed.
1 . A processor comprising:
an instruction unit to receive a single instruction, multiple thread (SIMT) instruction, the SIMT instruction having at least one field to provide at least one value, the at least one value to indicate a plurality of threads that are to execute the SIMT instruction; and
a SIMT processor coupled with the instruction unit, the SIMT processor to execute the SIMT instruction for each of the plurality of threads.
2 . The processor of claim 1 , wherein the at least one value is to indicate the plurality of threads as being only a subset of a plurality of threads configured for the processor.
3 . The processor of claim 1 , wherein the at least one value is to indicate the plurality of threads as being only a subset of a plurality of threads initialized to execute code including the SIMT instruction.
4 . The processor of claim 1 , wherein the SIMT processor includes a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently, and wherein the at least one value is to indicate that only a subset of the plurality of processing elements are to execute the SIMT instruction.
5 . The processor of claim 4 , wherein the subset is one of only a single thread, only half the plurality of processing elements, only one quarter the plurality of processing elements, or only one eighth the plurality of processing elements.
6 . The processor of claim 4 , wherein the plurality of threads of the parallel thread group are a warp or a wavefront.
7 . The processor of claim 1 , wherein the SIMT processor includes a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently, and wherein the at least one value is to indicate a number of times the plurality of processing elements are to execute the SIMT instruction sequentially.
8 . The processor of claim 1 , wherein the at least one value is to indicate only a subset of warps initialized to execute code including the SIMT instruction or only a subset of wavefronts initialized to execute code including the SIMT instruction.
9 . The processor of claim 1 , wherein the instruction unit is to receive a second SIMT instruction, the second SIMT instruction having at least one field to provide a source thread identifier and at least one field to provide a source register identifier.
10 . The processor of claim 9 , wherein a processing element of the SIMT processor is to execute the second SIMT instruction for a first thread to receive data from a register that is to be identified by the source register identifier of a second, different thread that is to be identified by the source thread identifier.
11 . The processor of claim 10 , wherein the second SIMT instruction has at least one field to provide a second source thread identifier and at least one field to provide a second source register identifier, and wherein the processing element is to execute the second SIMT instruction for the first thread to receive data from a second register that is to be identified by the second source register identifier of a third, different thread that is to be identified by the second source thread identifier.
12 . The processor of claim 10 , wherein the second SIMT instruction has at least one field to provide a destination thread identifier and at least one field to provide a destination register identifier, and wherein the processing element is to execute the second SIMT instruction for the first thread to store a result in a third register that is to be identified by the destination register identifier in a third, different thread that is to be identified by the destination thread identifier.
13 . A method comprising:
receiving a single instruction, multiple thread (SIMT) instruction, the SIMT instruction having at least one field providing at least one value, the at least one value indicating a plurality of threads that are to execute the SIMT instruction; and
executing the SIMT instruction for each of the plurality of threads on a SIMT processor.
14 . The method of claim 13 , wherein the at least one value indicates the plurality of threads as being only a subset of a plurality of threads configured and initialized to execute code including the SIMT instruction.
15 . The method of claim 13 , wherein the at least one value indicates that only a subset of a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently are to execute the SIMT instruction concurrently.
16 . The method of claim 13 , wherein the at least one value indicates a number of times a plurality of processing elements, which are to execute threads of a thread group concurrently, are to execute the SIMT instruction sequentially.
17 . The method of claim 13 , further comprising:
receiving a second SIMT instruction, the second SIMT instruction having at least one field providing a source thread identifier and at least one field providing a source register identifier; and
executing the second SIMT instruction with a processing element of a SIMT processor for a first thread to receive data from a register identified by the source register identifier of a second, different thread identified by the source thread identifier.
18 . A system comprising:
a processor comprising:
an instruction unit to receive a single instruction, multiple thread (SIMT) instruction, the SIMT instruction having at least one field to provide at least one value, the at least one value to indicate a plurality of threads that are to execute the SIMT instruction; and
a SIMT processor coupled with the instruction unit, the SIMT processor to execute the SIMT instruction for each of the plurality of threads; and
a dynamic random access memory (DRAM) coupled with the processor.
19 . The system of claim 18 , wherein the SIMT processor includes a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently, and wherein the at least one value is to indicate that only a subset of the plurality of processing elements are to execute the SIMT instruction.
20 . The system of claim 18 , wherein the SIMT processor includes a plurality of processing elements initialized to execute a plurality of threads of a parallel thread group concurrently, and wherein the at least one value is to indicate a number of times the plurality of processing elements are to execute the SIMT instruction sequentially.