Power management for multi-dimensional programmable logic devices

1. A system, comprising:

a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause performance of operations comprising:

receiving an indication of a logic design;

identifying an expected resource consumption of the logic design;

placing the logic design in a system design for an integrated circuit based at least in part on the expected resource consumption of the logic design;

determining that resource consumption of the logic design changed; and

adjusting placement of the logic design within the system design based on the resource consumption.

2. The system of claim 1 , comprising a programmable logic device, wherein the operations comprise:

generating a bitstream based at least in part on the system design; and

transmitting the bitstream to the programmable logic device to program the logic design in programmable logic fabric of the programmable logic device.

3. The system of claim 1 , comprising:

an integrated circuit die comprising a first portion of a power distribution network; and

an active interposer circuit comprising a second portion of the power distribution network, wherein the active interposer circuit is configured to regulate the first portion of the power distribution network, the second portion of the power distribution network, or both, after the active interposer circuit is programmed based at least in part on the system design.

4. The system of claim 1 , wherein the operations comprise:

generating a bitstream based at least in part on the system design;

transmitting the bitstream to a programmable logic device to program the logic design in programmable logic fabric of the programmable logic device;

receiving an indication of a temperature from a thermal sensor of the programmable logic device; and

adjusting the system design based at least in part on the temperature.

5. The system of claim 1 , wherein the operations comprise:

programming a device based at least in part on the system design; and

transmitting a toggling factor to the device, wherein the device comprises a controller configured to tune an intrinsic capacitance of the device based at least in part on the toggling factor.

6. The system of claim 5 , wherein the device comprises an active interposer, and wherein the controller controls switching of components included within the active interposer based at least in part on toggling factor.

7. The system of claim 1 , comprising a device having a controller, wherein the controller is configured to generate an artificial current during a duration of time corresponding to low activity of the device, and wherein the operations comprise:

programming the device based at least in part on the system design; and

transmitting an indication of a current amount corresponding to the low activity of the device.

8. The system of claim 1 , comprising a programmable logic device, wherein the operations comprise:

programming the programmable logic device by writing a fabric configuration bitstream to configuration memory of the programmable logic device, where the fabric configuration bitstream is generated based at least in part on the system design.

9. The system of claim 8 , wherein writing the fabric configuration bitstream involves the fabric configuration bitstream transmitting from a base die to the configuration memory through interface circuitry of the programmable logic device, wherein the fabric configuration bitstream comprises configuration instructions associated with selectively activating a device within programmable logic fabric of the programmable logic device, and wherein selectively activating the device changes an intrinsic capacitance of the programmable logic fabric.

10. The system of claim 9 , wherein the configuration instructions are further associated with regulating noise using the intrinsic capacitance of the programmable logic fabric.

11. A system, comprising:

a device having a controller, wherein the controller is configured to generate an artificial current during a duration of time corresponding to low activity of the device; and

a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause performance of operations comprising:

receiving an indication of a logic design;

identifying an expected resource consumption of the logic design;

placing the logic design in a system design for an integrated circuit based at least in part on the expected resource consumption of the logic design;

programming the device based at least in part on the system design; and

transmitting an indication of a current amount corresponding to the low activity of the device.

12. The system of claim 11 , wherein the operations comprise:

transmitting a toggling factor to the device, wherein the controller is configured to tune an intrinsic capacitance of the device based at least in part on the toggling factor.

13. The system of claim 12 , wherein the device comprises an active interposer, and wherein the controller controls switching of components included within the active interposer based at least in part on toggling factor.

14. The system of claim 11 , wherein the operations comprise:

programming the device by writing a fabric configuration bitstream to configuration memory of the device, where the fabric configuration bitstream is generated based at least in part on the system design.

15. A system, comprising:

a tangible, non-transitory, and machine-readable medium, comprising machine-readable instructions stored thereon that, when executed by a processor, cause performance of operations comprising:

receiving an indication of a logic design;

identifying an expected resource consumption of the logic design;

placing the logic design in a system design for an integrated circuit based at least in part on the expected resource consumption of the logic design;

generating a bitstream based at least in part on the system design;

transmitting the bitstream to a programmable logic device to program the logic design in programmable logic fabric of the programmable logic device;

receiving an indication of a temperature from a thermal sensor of the programmable logic device; and

adjusting the system design based at least in part on the temperature.

16. The system of claim 15 , wherein the operations comprise:

programming a device based at least in part on the system design; and

transmitting a toggling factor based on the temperature to the device, wherein the device comprises a controller configured to tune an intrinsic capacitance of the device based at least in part on the toggling factor.

17. The system of claim 16 , wherein the device comprises an active interposer, and wherein the controller controls switching of components included within the active interposer based at least in part on toggling factor.

18. The system of claim 15 , comprising a device having a controller, wherein the controller is configured to generate an artificial current during a duration of time corresponding to low activity of the device, and wherein the operations comprise:

programming the device based at least in part on the system design; and

transmitting an indication of a current amount corresponding to the low activity of the device.

19. The system of claim 15 , comprising the programmable logic device, wherein the operations comprise:

programming the programmable logic device by writing a fabric configuration bitstream to configuration memory of the programmable logic device, where the fabric configuration bitstream is generated based at least in part on the system design.

20. The system of claim 19 , wherein writing the fabric configuration bitstream involves the fabric configuration bitstream transmitting from a base die to the configuration memory through interface circuitry of the programmable logic device, wherein the fabric configuration bitstream comprises configuration instructions associated with selectively activating a device within the programmable logic fabric of the programmable logic device, and wherein selectively activating the device changes an intrinsic capacitance of the programmable logic fabric.