Context-sensitive overhead processor
View Patent ↗An overhead processor for data transmission in digital communications is disclosed. Incoming data is transmitted along a datapath. If there are two or more groups of incoming data, arriving separately, the initial group(s) of received data can be held in an elastic store until the arrival of additional group(s) of data, and upon the arrival of additional group(s) of data, all received data are combined and transmitted into flip-flop(s). The data is transmitted from said flip-flop(s) to a logic element to determine the new data context of imminent incoming data prior to any additional incoming bytes arriving along the datapath. Therefore, the number of overhead processors required for multi-byte data transmission is reduced, potentially reducing the number of required overhead processors in digital communications to 1.
1. A context sensitive overhead processor for transmitting data, the processor comprising instructions enabling the processor to:
receive, on a datapath, data associated with a state machine, wherein the received data comprises overhead bytes associated with a context;
receive, from storage circuitry, a first state associated with the state machine, wherein the first state comprises the context; and
compute, based on the received data and the first state, a second state associated with the state machine.
2. The processor of claim 1 , wherein the received data and the received first state are received by the processor in a single clock cycle.
3. The processor of claim 1 , wherein the storage circuitry comprises an elastic store.
4. The processor of claim 1 , wherein the processor further comprises instructions enabling the processor to store the second state using the storage circuitry.
5. The processor of claim 3 , wherein the storage circuitry comprises a flip-flop.
6. The processor of claim 5 , wherein the elastic storage stores a first group of data; and
the first group of data is read by the flip-flop.
7. The processor of claim 5 , wherein:
the elastic storage stores a first group of data;
the elastic storage stores a second group of data;
the first group of data and the second group of data are combined; and
the combined group of data are read by the flip-flop.
8. A method for transmitting data using a context sensitive overhead processor, the method comprising:
receiving, on a datapath, data associated with a state machine, wherein the received data comprises overhead bytes associated with a context;
receiving, from storage circuitry, a first state associated with the state machine, wherein the first state comprises the context; and
computing, based on the received data and the first state, a second state associated with the state machine.
9. The method of claim 8 , wherein the received data and the received first state are received by the processor in a single clock cycle.
10. The method of claim 8 , wherein the storage circuitry comprises an elastic store.
11. The method of claim 8 further comprising storing the second state using the storage circuitry.
12. The method of claim 10 , wherein the storage circuitry comprises a flip-flop.
13. The method of claim 12 further comprising:
storing, in the elastic storage, a first group of data; and
reading, using the flip-flop, the first group of data.
14. The method of claim 12 further comprising:
storing, in the elastic storage, a first group of data;
storing, in the elastic storage, a second group of data;
combining the first group of data and the second group of data; and
reading, using the flip-flop, the combined group of data.
15. A context sensitive overhead processor for transmitting data, the processor configured to:
receive, from storage circuitry, a first state associated with a state machine, wherein the first state comprises a first context;
receive, on a datapath, data associated with the state machine, wherein the data comprises overhead bytes associated with the first context; and
compute, based on the received data and the first state, a second state associated with the state machine, wherein the second state comprises a second context.
16. The processor of claim 15 , wherein the received data and the received first state are received by the processor in a single clock cycle.
17. The processor of claim 15 , wherein:
the storage circuitry comprises an elastic storage, and wherein the elastic storage stores a first group of data;
the storage circuitry comprises a flip-flop, and wherein the first group of data is read by the flip-flop.
18. The processor of claim 15 , wherein:
the storage circuitry comprises an elastic storage, and wherein the elastic storage stores a first group of data and a second group of data, and wherein the first group of data and the second group of data are combined; and
the storage circuitry comprises a flip-flop, and wherein the combined group of data is read by the flip-flop.