Three-dimensional columnar input-output (IO) circuitry for integrated circuit device
This disclosure is directed to methods of disaggregating columnar IO operations from a programmable logic fabric using 3-D packaging technology. More specifically, methods of 3-D programmable fabric arrangements that include one or more IO chiplets stacked in a 3-D orientation on a programmable logic fabric main die that includes one or more D2D drivers to enable communication between the one or more IO chiplets and the programmable logic fabric main die. The IO chiplets may be coupled to the programmable fabric main die through connection to the one or more D2D drivers arranged on the programmable fabric main die.
1 . A system comprising:
one or more input/output (IO) chiplets;
a programmable fabric main die, wherein the one or more IO chiplets are stacked in a three-dimensional orientation above or below the programmable fabric main die, and wherein the programmable fabric main die comprises:
one or more die-to-die (D2D) drivers embedded within the programmable fabric main die, wherein the one or more D2D drivers interface with the one or more IO chiplets; and
a plurality of sectors associated with logic of the programmable fabric main die, wherein a location of the one or more D2D drivers within a sector of the plurality of sectors of the programmable fabric main die is based on logic of the sector of the plurality of sectors.
2 . The system of claim 1 , wherein the one or more D2D drivers are embedded into the programmable fabric main die in a vertical configuration in relation to vertical interconnection resources of the programmable fabric main die from a bottom edge of the programmable fabric main die to a top edge of the programmable fabric main die.
3 . The system of claim 1 , wherein the one or more D2D drivers are embedded into the programmable fabric main die in a horizontal configuration in relation to vertical interconnection resources of the programmable fabric main die from a left edge of the programmable fabric main die to a right edge of the programmable fabric main die.
4 . The system of claim 1 , wherein the one or more IO chiplets are coupled to the programmable fabric main die at one or more locations corresponding to the location of the one or more D2D drivers on the programmable fabric main die.
5 . The system of claim 1 , wherein the one or more IO chiplets comprise IO drivers that are larger than the one or more D2D drivers.
6 . The system of claim 1 , wherein the one or more IO chiplets comprise through silicon vias (TSVs) and copper pillars, wherein the through silicon vias (TSVs) and copper pillars connect via one or more connection interfaces to the programmable fabric main die, to couple the programmable fabric main die to the one or more IO chiplets.
7 . The system of claim 1 , wherein the programmable fabric main die comprises a field-programmable gate array (FPGA).
8 . The system of claim 1 , wherein the programmable fabric main die comprises a plurality of sectors associated with logic of the programmable fabric main die.
9 . The system of claim 8 , wherein some sectors of the plurality of sectors are connected to a greater number of IO chiplets than other sectors of the plurality of sectors.
10 . A programmable fabric main die, wherein one or more IO chiplets are stacked in a three-dimensional orientation above or below the programmable fabric main die, and wherein the programmable fabric main die comprises:
one or more die-to-die (D2D) drivers embedded within the programmable fabric main die, wherein the one or more D2D drivers interface with the one or more IO chiplets; and
a plurality of sectors associated with logic of the programmable fabric main die, wherein some sectors of the plurality of sectors are connected to a greater number of IO chiplets than other sectors of the plurality of sectors.
11 . The programmable fabric main die of claim 10 , wherein the one or more IO chiplets comprise IO drivers that are larger than the one or more D2D drivers.
12 . The programmable fabric main die of claim 10 , wherein the one or more D2D drivers are embedded into the programmable fabric main die in a vertical configuration in relation to vertical interconnection resources of the programmable fabric main die.
13 . The programmable fabric main die of claim 10 , wherein the one or more D2D drivers are embedded into the programmable fabric main die in a horizontal configuration in relation to vertical interconnection resources of the programmable fabric main die.
14 . The programmable fabric main die of claim 10 , wherein the one or more D2D drivers interface with the one or more IO chiplets via a plurality of microbumps or hybrid bonds.
15 . An integrated circuit comprising:
one or more input/output (IO) chiplets;
a programmable fabric main die, wherein the one or more IO chiplets are stacked in a three-dimensional orientation above or below the programmable fabric main die, and wherein the programmable fabric main die comprises:
one or more die-to-die (D2D) drivers embedded within the programmable fabric main die, wherein the one or more D2D drivers interface with the one or more IO chiplets; and
a plurality of sectors associated with logic of the programmable fabric main die, wherein a location of the one or more D2D drivers within a sector of the plurality of sectors of the programmable fabric main die is based on logic of the sector of the plurality of sectors.
16 . The integrated circuit of claim 15 , wherein the programmable fabric main die does not include IO resources within the programmable fabric main die.
17 . The integrated circuit of claim 15 , wherein the programmable fabric main die does include IO resources within the programmable fabric main die.
18 . The integrated circuit of claim 15 , wherein the one or more D2D drivers are less than 1.0 square microns in area.
19 . The integrated circuit of claim 15 , wherein the programmable fabric main die comprises a plurality of sectors associated with logic of the programmable fabric main die.
20 . The integrated circuit of claim 19 , wherein some sectors of the plurality of sectors are connected to a greater number of IO chiplets than other sectors of the plurality of sectors.