Granted Patent B2

US 8,199,782 · App. 12/488,836 · Granted Jun 12, 2012

Abstract

Claims (34)

1. A system for detecting skew across a plurality of transmitting lanes in a high-speed data transmission system, the system comprising:

a communication circuitry;

(a) a plurality of data transmitted by the communication circuitry as a plurality of frames across the plurality of transmitting lanes, wherein each of said plurality of transmitting lanes is coupled to one of a plurality of framers;

(b) a frame start signal detected in said plurality of data by said plurality of framers, wherein said frame start signal indicates a starting bit of each of said plurality of frames; and

(c) a frame synchronization signal detected in said plurality of frames by said plurality of framers, wherein said frame synchronization signal indicates an origin of each of said plurality of transmitting lanes in said plurality of data, wherein the system detects skew between said plurality of transmitting lanes using the frame start signal and the frame synchronization signal.

2. The system of claim 1 , further comprising a plurality of buffers, wherein each of said plurality of buffers is coupled to one of said plurality of framers.

3. The system of claim 2 , wherein said frame start signal and said frame synchronization signal indicate to said plurality of framers a location associated with each of said plurality of buffers.

4. The system of claim 3 , wherein said plurality of buffers are a plurality of First-In-First-Out (FIFO) buffers.

5. The system of claim 4 , further comprising an aggregator that outputs said plurality of data.

6. The system of claim 5 , further comprising a multiplexer located within said aggregator.

7. The system of claim 6 , wherein said multiplexer re-combines said plurality of transmitting lanes into a single transmitting lane.

8. The system of claim 7 , wherein said multiplexer is located next to said plurality of buffers.

9. The system of claim 7 , wherein said aggregator reads said single transmitting lane out of said multiplexer.

10. A system for correcting skew across a plurality of transmitting lanes in a high-speed data transmission system, the system comprising:

(a) a plurality of data transmitted as a plurality of frames across the plurality of transmitting lanes, wherein each of said plurality of transmitting lanes is coupled to one of a plurality of framers;

(b) a frame start signal detected in said plurality of data by said plurality of framers, wherein said frame start signal indicates a starting bit of each of said plurality of frames;

(c) a frame synchronization signal detected in said plurality of data by said plurality of framers, wherein said frame synchronization signal indicates an origin of each of said plurality of transmitting lanes in said plurality of data; and

(d) a plurality of buffers, wherein each of said plurality of buffers is coupled to one of said plurality of framers, wherein said frame start signal and said frame synchronization signal indicate to said plurality of framers a skew offsetting bit location in each of said plurality of buffers to begin writing said plurality of data, thereby allowing said plurality of framers to write said plurality of data into said plurality of buffers with said plurality of transmitting lanes in alignment.

11. The system of claim 10 , wherein said plurality of buffers are a plurality of First-In-First-Out (FIFO) buffers.

12. The system of claim 10 , further comprising an aggregator that outputs said plurality of data.

13. The system of claim 12 , further comprising a multiplexer located within said aggregator.

14. The system of claim 13 , wherein said multiplexer re-combines said plurality of transmitting lanes into a single transmitting lane.

15. The system of claim 14 , wherein said multiplexer is located next to said plurality of buffers.

16. A system for transmitting data in a multiple lane distribution system in a high-speed data transmission system, the system comprising:

(a) a plurality of data transmitted as a plurality of frames in a single transmitting lane, wherein said transmitting lane is divided into a plurality of transmitting lanes by a de-multiplexer, thereby dividing said plurality of data across said plurality of transmitting lanes, wherein each of said plurality of transmitting lanes is coupled to one of a plurality of framers, wherein said plurality of data is fed into said plurality of framers;

(b) a frame start signal detected in said plurality of data by said plurality of framers, wherein said frame start signal indicates a starting bit of each of said plurality of frames;

(c) a frame synchronization signal detected in said plurality of data by said plurality of framers, wherein said frame synchronization signal indicates an origin of each of said plurality of transmitting lanes in said plurality of data;

(d) a plurality of buffers, wherein each of said plurality of buffers is coupled to one of said plurality of framers, wherein said frame start signal and said frame synchronization signal indicate to said plurality of framers a skew offsetting bit location in each of said plurality of buffers to begin writing said plurality of data, thereby allowing said plurality of framers to write said plurality of data into said plurality of buffers with said plurality of transmitting lanes in alignment;

(e) a multiplexer, wherein said multiplexer re-combines said plurality of transmitting lanes into said single transmitting lane; and

(f) a aggregator, wherein said aggregator outputs said plurality of data as said single transmitting lane.

17. The system of claim 16 , wherein said multiplexer is located within said aggregator, whereby said aggregator reads said plurality of data out of said plurality of buffers, said multiplexer located within said aggregator recombines said plurality of data, and said aggregator outputs said plurality of data as said single transmitting lane.

18. The system of claim 16 , wherein said multiplexer is located next to said plurality of buffers, whereby said multiplexer reads said plurality of data out of said plurality of buffers and recombines said plurality of data into said single transmitting lane.

19. The system of claim 18 , wherein said aggregator reads said single transmitting lane out of said multiplexer and outputs said single transmitting lane.

20. The system of claim 1 , wherein said plurality of buffers are a plurality of First-In-First-Out (FIFO) buffers.

Assignments (10)