Distributed double-precision floating-point addition

1. A system for a double-precision floating-point sum of two double-precision floating-point numbers, comprising:

a first processing circuit that receives a first subset of each of the two double-precision floating-point numbers and generates a control signal, a data signal indicating shifted values of one or both of the two double-precision floating-point numbers, and a first portion of the double-precision floating-point sum based at least in part on the first subset of each of the two double-precision floating-point numbers, wherein the first subset of each of the two double-precision floating-point numbers comprises:

a first portion of a first mantissa of a first double-precision floating-point number of the two double-precision floating-point numbers;

a second portion of a second mantissa of a second double-precision floating-point number of the two double-precision floating-point numbers, wherein the first portion of the first mantissa and the first portion of the second mantissa have corresponding locations within their respective floating-point numbers;

a first exponent of the first double-precision floating-point number of the two double-precision floating-point numbers; and

a second exponent of the second double-precision floating-point number of the two double-precision floating-point numbers;

a second processing circuit that receives a second subset of each of the two double-precision floating-point numbers and generates a carry signal and a second portion of the double-precision floating-point sum based at least in part on the second subset of each of the two double-precision floating-point numbers, wherein the second subset of each of the two double-precision floating-point numbers comprises:

a second portion of the first mantissa;

a second portion of a second mantissa;

the first exponent; and

the second exponent; and

a bidirectional cascade chain that couples to the first and second processing circuits and that:

conveys the control signal from the first processing circuit to the second processing circuit,

conveys the data signal from the first processing circuit to the second processing circuit, and

conveys the carry signal from the second processing circuit to the first processing circuit.

2. The system of claim 1 , wherein the first portion of the first mantissa comprises most significant bits of the first mantissa, and the first portion of the second mantissa comprises most significant bits of the second mantissa.

3. The system of claim 2 , wherein a first number of the most significant bits in the first portion of the first mantissa is the same as a second number of the most significant bits in the first portion of the second mantissa.

4. The system of claim 1 , wherein the second portion of the first mantissa comprises least significant bits of the first mantissa, and the second portion of the second mantissa comprises least significant bits of the second mantissa.

5. The system of claim 4 , wherein a first number of the least significant bits in the second portion of the first mantissa is the same as a second number of least significant bits in the second portion of the second mantissa.

6. The system of claim 1 , wherein the first processing circuit comprises:

configurable interconnect circuitry that selects the first double-precision floating-point number of the two double-precision floating-point numbers based at least in part on the control signal, wherein the control signal indicates that the first double-precision floating-point number is smaller than the second double-precision floating-point number of the two double-precision floating-point numbers; and

a right shifter that generates a right shifted signal by shifting a portion of the selected first double-precision floating-point number by a predetermined number of bits to the right.

7. The system of claim 6 , wherein the first processing circuit comprises an adder circuit that adds the carry signal and the right shifted signal to a corresponding portion of the second double-precision floating-point number, and wherein the adder circuit generates a partial mantissa signal.

8. The system of claim 7 , wherein the first processing circuit comprises a normalization circuit that shifts the partial mantissa signal an additional predetermined number of bits to the left to generate a normalized mantissa.

9. A method for operating first and second specialized processing blocks that are arranged in a bidirectional cascade chain to generate a double-precision floating-point sum, comprising:

receiving, at a first processing circuit, a first subset of a first double-precision floating-point number and a first subset of a second double-precision floating-point number, wherein the first subsets of the first and second double-precision floating-point numbers comprises:

a first portion of a first mantissa of the first double-precision floating-point number;

a second portion of a second mantissa of the second double-precision floating-point number, wherein the first portion of the first mantissa and the first portion of the second mantissa have corresponding locations within their respective floating-point numbers;

a first exponent of the first double-precision floating-point number; and

a second exponent of the second double-precision floating-point number;

determining, using the first subset of the first double-precision floating-point number and the first subset of the second double-precision floating-point number whether the first double-precision floating-point number or the second double-precision floating-point number is larger;

generating, using the first processing circuit, a control signal indicating that the first double-precision floating-point number is larger than the second double-precision floating-point number;

generating, using the first processing circuit, a data signal indicating shifted values of the first or second double-precision floating-point number, and a first partial sum that is based at least in part on the first subset of the first double-precision floating-point number and the first subset of the second double-precision floating-point number;

receiving a second subset of the first double-precision floating-point number and a second subset of the second double-precision floating-point number at a second processing circuit, wherein the second subsets of the first and second double-precision floating-point numbers comprises:

a second portion of the first mantissa;

a second portion of a second mantissa;

the first exponent; and

the second exponent; and

generating, using the second processing circuit, a carry signal and a second partial sum that is based at least in part on the second subset of the first double-precision floating-point number and the second subset of the second double-precision floating-point number.

10. The method of claim 9 , comprising sending the control signal from the first processing circuit to the second processing circuit.

11. The method of claim 9 , comprising sending the data signal from the first processing circuit to the second processing circuit.

12. The method of claim 9 , comprising sending the carry signal from the second processing circuit to the first processing circuit.

13. An integrated circuit that generates a double-precision floating-point sum of first and second double-precision floating-point numbers, comprising:

a cascade chain that interconnects a plurality of processing circuitries; and

the plurality of processing circuitries, wherein a first processing circuitry of the plurality of processing circuitries receives a first portion of the first double-precision floating-point number and a first portion of the second double-precision floating-point number, wherein the first processing circuitry is selectively operated in a first mode or second mode, wherein the first mode comprises the first processing circuitry:

receiving a first carry signal over the cascade chain;

generating a first control signal indicating whether the first double-precision floating-point number or the second double-precision floating-point number is larger;

generating a first data signal indicating shifted values of the first or second double-precision floating-point numbers; and

generating most significant bits (MSBs) of the double-precision floating-point sum based at least in part on the first carry signal, and

transmitting the first control signal and the first data signal; and

the second mode comprises the first processing circuitry:

receiving a second control signal from a second processing circuitry of the plurality of processing circuitries;

generating a second carry signal; and

generating least significant bits (LSBs) of the double-precision floating-point sum based at least in part on the second control signal.

14. The integrated circuit of claim 13 , wherein the cascade chain comprises a bidirectional cascade chain that comprises:

at least one first cascade connection in a first direction from the first processing circuitry to the second processing circuitry; and

at least one second cascade connection in a second direction from the second processing circuitry to the first processing circuitry.

15. The integrated circuit of claim 13 , wherein the second mode comprises the second processing circuitry:

generating a second data signal based on the second carry signal.

16. The integrated circuit of claim 13 , wherein, in the first mode of the first processing circuitry, the first portion comprises:

a first exponent corresponding to the first double-precision floating-point number;

a second exponent corresponding to the second double-precision floating-point number;

a first MSB portion of a mantissa of the first double-precision floating-point number; and

a second MSB portion of a mantissa of the second double-precision floating-point number.

17. The integrated circuit of claim 14 , wherein the second processing circuitry receives:

a first exponent corresponding to the first double-precision floating-point number;

a second exponent corresponding to the second double-precision floating-point number;

a first LSB portion of a mantissa of the first double-precision floating-point number; and

a second LSB portion of a mantissa of the second double-precision floating-point number.

18. The integrated circuit of claim 13 , wherein, in the second mode of the first processing circuitry, the first portion comprises:

a first exponent corresponding to the first double-precision floating-point number;

a second exponent corresponding to the second double-precision floating-point number;

a first LSB portion of a mantissa of the first double-precision floating-point number; and

a second LSB portion of a mantissa of the second double-precision floating-point number.