Orthogonal multi-phase scheduling circuitry
An integrated circuit may include orthogonal multi-phase scheduling circuitry. The scheduling circuitry may include a number of orthogonal scheduling circuits each of which is configured to receive different command types and to output a single winning command. The scheduling circuitry may further include a phase assignment circuit for receiving the winning commands from the orthogonal scheduling circuits and for assigning the received winning commands to different corresponding phase groups. Each orthogonal scheduling circuit may include command buffers, command arbiters, a global arbiter, and associated safe checking circuits.
1. A method comprising:
using an interface circuit in an integrated circuit to communicate with a device external to the integrated circuit;
outputting a first type of command from command scheduling circuitry in the integrated circuit only during a first phase of each clock cycle of an internal clock signal, wherein the command scheduling circuitry is controlled by the internal clock signal;
outputting a second type of command from the command scheduling circuitry only during a second phase of each clock cycle of the internal clock signal that is different than the first phase; and
outputting a third type of command from the command scheduling circuitry only during a third phase of each clock cycle of the internal clock signal that is different than the first phase and the second phase.
2. The method of claim 1 further comprising:
outputting a fourth type of command from the command scheduling circuitry only during a fourth phase of each clock cycle of the internal clock signal that is different than the first phase, the second phase, and the third phase.
3. An integrated circuit, comprising:
an interface circuit operable to communicate with a device external to the integrated circuit; and
command scheduling circuitry controlled by an internal clock signal, wherein the command scheduling circuitry is configured to output at least a first type of command, a second type of command, and a third type of command, and wherein the command scheduling circuitry is further configured to output the first type of command only during a first phase of each clock cycle of the internal clock signal, to output the second type of command only during a second phase of each clock cycle of the internal clock signal that is different than the first phase, and to output the third type of command only during a third phase of each clock cycle of the internal clock signal that is different than the first phase and the second phase.
4. The integrated circuit of claim 3 , wherein the command scheduling circuitry is further configured to output at least four different types of commands during at least four different phases of each clock cycle of the internal clock signal.
5. The integrated circuit of claim 3 , wherein the command scheduling circuitry comprises a plurality of scheduling circuits each of which is configured to receive commands of different types and to output a single winning command.
6. The integrated circuit of claim 3 , wherein the command scheduling circuitry comprises a plurality of independent scheduling circuits such that no safe checking is required between commands in different phases of the internal clock signal.
7. The integrated circuit of claim 3 , wherein the command scheduling circuitry comprises a plurality of dependent scheduling circuits such that safe checking is required between commands in different phases of the internal clock signal.
8. An integrated circuit, comprising:
an interface circuit configured to communicate with an external device; and
multi-phase scheduling circuitry controlled by an internal clock signal, wherein the multi-phase scheduling circuitry is configured to output a first type of command only during a first phase of each clock cycle of the internal clock signal, to output a second type of command only during a second phase of each clock cycle of the internal clock signal that is different than the first phase, and to output a third type of command only during a third phase of each clock cycle of the internal clock signal that is different than the first phase and the second phase.
9. The integrated circuit of claim 8 , wherein the multi-phase scheduling circuitry is further configured to receive commands of the first type and to output the commands of the first type only during the first phase of each clock cycle of the internal clock signal.
10. The integrated circuit of claim 9 , wherein the multi-phase scheduling circuitry is further configured to receive commands of the second type and to output the commands of the second type only during the second phase of each clock cycle of the internal clock signal.
11. The integrated circuit of claim 8 , wherein the multi-phase scheduling circuitry outputs a fourth type of command only during a fourth phase of each clock cycle of the internal clock signal that is different than the first phase, the second phase, and the third phase.
12. The integrated circuit of claim 8 , wherein the multi-phase scheduling circuitry comprises a plurality of scheduling circuits.
13. The integrated circuit of claim 12 , wherein each scheduling circuit in the plurality of scheduling circuits is configured to receive commands of different types.
14. The integrated circuit of claim 12 , wherein each scheduling circuit in the plurality of scheduling circuits is configured to output a single winning command at any given point in time.
15. The integrated circuit of claim 12 , wherein the multi-phase scheduling circuitry further comprises:
a phase assignment circuit configured to assign the first type of command to the first phase of each clock cycle of the internal clock signal and to assign the second type of command to the second phase of each clock cycle of the internal clock signal.
16. The integrated circuit of claim 15 , wherein the phase assignment circuit is further configured to assign at least one no-operation (NOP) to at least one empty phase of the internal clock signal.
17. The integrated circuit of claim 12 , wherein at least one scheduling circuit in the plurality of scheduling circuits comprises:
a plurality of command queues configured to receive and buffer input commands of different types.
18. The integrated circuit of claim 17 , wherein the at least one scheduling circuit in the plurality of scheduling circuits further comprises:
a plurality of command arbiters configured to receive first output commands from the plurality of command queues.
19. The integrated circuit of claim 18 , wherein the at least one scheduling circuit in the plurality of scheduling circuits further comprises:
a global arbiter configured to receive second output commands from the plurality of command arbiters and to output a single winning command from among the second output commands received from the plurality of command arbiters.
20. The integrated circuit of claim 19 , wherein the at least one scheduling circuit in the plurality of scheduling circuits further comprises:
a plurality of safe checking circuits configured to monitor the single winning command output from the global arbiter.