IP Library Patent Application 13947134
Patent Application
App. No. 13/947,134

Eye pattern generation of unequalized eye patterns using a serial receiver with embedded eye capability

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Quick Facts
Patent No.
US None
App. No.
13/947,134
Abstract

The use of eye pattern circuitry associated with a serial receiver embedded in an integrated circuit (e.g. in an FPGA) relies on the signal quality and signal frequency being sufficient for the serial receiver to lock onto the signal: if this is not possible then it is not possible to obtain an eye pattern. Our novel invention enables the use of this embedded circuitry where the signal quality and signal frequency are not sufficient by splitting the incoming signal, then using the clock recovered with further processing from one of the split signals together with the built-in eye pattern circuitry to obtain a realistic eye pattern for the unprocessed signal, regardless of the quality of that unprocessed signal. The technique uses the free-running or ‘slave’ mode of these serial receivers in which the receiver does not lock to the incoming data. To date, this mode has been used for oversampling but not for sampling at the actual data rate with a recovered clock in order obtain eye pattern samples.

Claims (15)

1 . Eye pattern generating apparatus comprising:

a serial data stream signal splitter which generates two or more output versions of its input serial data stream

and a signal conditioning circuit applied to the serial data stream derived from the first output of the serial data stream signal splitter to produce a conditioned signal

and a “master” serial receiver or any clock recovery device to recover a clock from the conditioned signal

and a “slave” serial receiver with integrated eye pattern capability which derives its timing reference from the clock recovered by the “master” serial receiver or clock recovery device and the “slave” serial receiver produces eye pattern data from a non-conditioned signal which is derived from the second output of the serial data stream signal splitter.

2 . Eye pattern generating apparatus comprising:

a serial data stream signal splitter which generates two or more output versions of its input serial data stream

and a “master” serial receiver or any clock recovery device to recover a clock from the first output of the serial data stream signal splitter

and a “slave” serial receiver with integrated eye pattern capability which derives its timing reference from the clock recovered by the “master” serial receiver or clock recovery device and the “slave” serial receiver produces eye pattern data from the second output of the serial data stream signal splitter.

3 . Eye pattern generating apparatus comprising:

a “master” serial receiver or any clock recovery device used to recover a clock from a serial data signal

and a “slave” serial receiver with integrated eye pattern capability which derives its timing reference from the clock recovered by the “master” serial receiver or clock recovery device and the “slave” serial receiver produces eye pattern data from a second serial data signal.

4 . The apparatus of claim 1 where eye pattern data is taken from both the “master” serial receiver or clock recovery device and the “slave” serial receiver and a comparison made to determine the effect of the signal conditioning circuit on the quality of the signal presented to the “master” serial receiver or clock recovery device.

5 . The apparatus of claim 1 where eye pattern data is taken from both the “master” serial receiver or clock recovery device and the “slave” serial receiver and a comparison made to determine the effect of the signal conditioning circuit on the delay and phase of the signal presented to the “master” serial receiver or clock recovery device.

6 . The apparatus of claim 3 where eye pattern data is taken from both the “master” serial receiver or clock recovery device and the “slave” serial receiver and a comparison made to determine the similarities and differences between two serial data signals.

Assignments (3)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 19, 2019
From: IMAGE PROCESSING TECHNIQUES LIMITED
To: INTEL CORPORATION
Reel/Frame 050093/0640 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 13, 2014
From: HUNTLEY, ALEXANDER NEIL; FAWCETT, ROGER
To: IMAGE PROCESSING TECHNIQUES LIMITED
Reel/Frame 034168/0417 →