Die to die interconnect structure for modularized integrated circuit devices

1. An integrated circuit system, comprising:

a first die comprising:

a first row of components disposed adjacent to a shoreline of the first die comprising a first portion of a time-division multiplexing (TDM) interface and a first portion of programmable fabric circuitry; and

a second row of components disposed adjacent to the first row of components and further away from the shoreline of the first die than the first row of components, wherein the second row of components comprises a second portion of the TDM interface and a second portion of the programmable fabric circuitry; and

a second die comprising a modular periphery intellectual property (IP) tile, wherein the second die is communicatively coupled to the first die via a modular interface, wherein the modular interface is configurable to

enable communication between a first microbump of the first die and a second microbump of the second die via the TDM interface.

2. The integrated circuit system of claim 1 , wherein communication between the first die and the second die occurs without traversing a network-on-chip.

3. The integrated circuit system of claim 1 , wherein the modular periphery IP tile is configurable to perform a function associated with the programmable fabric circuitry.

4. The integrated circuit system of claim 1 , wherein the modular interface is configurable to enable communication by applying a TDM technique or a wire-to-wire connection based at least in part on a configuration bitstream stored in configuration random access memory bits of the first die.

5. The integrated circuit system of claim 4 , wherein the TDM technique comprises a 2:1 TDM between the modular periphery IP tile and the programmable fabric circuitry, and wherein the TDM technique enables synchronous data transfer.

6. The integrated circuit system of claim 4 , wherein the communication comprises applying the TDM technique to data transmitted by a first microbump of the first die to a second microbump of the second die via a silicon interposer, wherein applying the TDM technique comprises accelerating the data from a single data rate to a double data rate.

7. The integrated circuit system of claim 4 , wherein the communication comprises applying the TDM technique to data transmitted by a first microbump of the second die to a second microbump of the first die via a silicon interposer, wherein applying the TDM technique comprises decelerating the data from a double data rate to a single data rate.

8. The integrated circuit system of claim 1 , wherein first die comprises:

data selection circuitry configurable to receive data processed by the programmable fabric circuitry;

a communication IP interface configurable to receive the data from the data selection circuitry, wherein the communication IP interface comprises:

a TDM structure configurable to enable the communication between the first die and the second die; and

a bypass connection configurable to enable a wire-to-wire connection by bypassing the TDM structure.

9. The integrated circuit system of claim 8 , wherein the TDM structure comprises:

a first circuit configurable to modify a data run rate from a single data rate to a double data rate in response to the data being communicated from the first die to the second die, wherein the first die operates at a slower clock speed; and

a second circuit configurable to modify the data run rate from the double data rate to the single data rate in response to the data being communicated from the second die to the first die.

10. The integrated circuit system of claim 1 , wherein the modular interface is configurable to:

enable communication between the first die and a third die without traversing a network-on-chip, wherein the third die comprises another modular periphery IP tile, wherein the other modular periphery IP tile is configurable to perform another function in association with the programmable fabric circuitry; and

enable communication between the first die and the third die using a wire-to-wire connection.

11. A method for programming a modularized integrated circuit system, comprising:

generating, via a design software, a higher-level circuit design for implementation on the modularized integrated circuit system;

generating, via the design software, a lower-level circuit design configuration based at least on the higher-level circuit design;

loading, via the design software, the lower-level circuit design onto the modularized integrated circuit system; and

configuring, via the design software, a modular interface between dies of the modularized integrated circuit system to have a first number of connections between the dies in response to implementing a time division multiplexing (TDM) interface configurable to facilitate communication between microbumps of the dies using a TDM technique, a second number of connections between the dies in response to not implementing the TDM interface, wherein the first number is greater than the second number.

12. The method of claim 11 , wherein configuring the modular interface comprises accelerating data communicated between the dies from a single data rate to a double data rate using the TDM interface, wherein the data is communicated from a first die to a second die comprising a faster clock rate than a clock rate of the first die.

13. The method of claim 11 , wherein configuring the modular interface comprises decelerating data communicated between the dies from a double data rate to a single data rate using the TDM interface, wherein the data is communicated from a first die to a second die comprising a slower clock rate than a clock rate of the first die.