Interface for efficient usage of communication circuitry
View Patent ↗Communication circuitry having efficient utilization of transceiver and channel resources is described. The communication circuitry may dynamically reallocate transceiver resources assigned to protocol circuitry, such that it becomes available for other circuitry or for the interface of the transceiver circuitry. Multiplexers of the transceiver circuitry may be used in the reallocation of resources.
1. Transceiver circuitry comprising:
a first transceiver coupled to a first communication channel;
protocol circuitry coupled to a first interface of the transceiver circuitry, wherein the protocol circuitry is configured to implement a communication protocol; and
a first multiplexer that selectably couples the first transceiver either to:
the first interface of the transceiver circuitry via the protocol circuitry; or
a second interface of the transceiver circuitry via a second multiplexer coupled to the first multiplexer and to the second interface of the transceiver circuitry, wherein the second multiplexer couples the first transceiver to the second interface of the transceiver circuitry.
2. The transceiver circuitry of claim 1 , comprising a second transceiver selectably coupled to the second interface via the second multiplexer.
3. The transceiver circuitry of claim 2 , wherein the second multiplexer receives a coded signal comprising a first instruction for the first transceiver and a second instruction for the second transceiver, and wherein the second multiplexer provides the first instruction to the first multiplexer and the second instruction to the second transceiver.
4. The transceiver circuitry of claim 1 , wherein the first multiplexer and the second multiplexer are coupled via a multiplexer bus.
5. The transceiver circuitry of claim 1 , comprising a multiplexer controller that controls whether the first multiplexer couples the first transceiver to either the protocol circuitry or the second interface.
6. The transceiver circuitry of claim 5 , wherein the multiplexer controller configures the first multiplexer coupling based on a determination that the first transceiver is unused by the protocol circuitry.
7. The transceiver circuitry of claim 1 , comprising an interconnect bridge interface that comprises the first interface and the second interface.
8. A system comprising:
a programmable logic device die;
an interconnect bridge comprising a plurality of channels and coupled to the programmable logic device die; and
transceiver circuitry comprising:
an interconnect bridge interface coupled to the interconnect bridge comprising a first plurality of channel interfaces and a second plurality of channel interfaces;
protocol circuitry configured to implement a communication protocol and coupled to the first plurality of channel interfaces of the interconnect bridge interface;
a first set of transceivers;
a second set of transceivers; and
a first set of multiplexers that selectably couples the first set of transceivers to:
the second plurality of channel interfaces via a second set of multiplexers; or
the first plurality of channel interfaces via the protocol circuitry;
wherein the second set of multiplexers selectably couples the second plurality of channel interfaces to the first set of multiplexers or to the second set of transceivers.
9. The system of claim 8 , wherein the number of transceivers in the first set of transceivers is the same as to the number of multiplexers in the first set of multiplexers.
10. The system of claim 8 , comprising a set of channel ports coupled to the first set of transceivers.
11. The system of claim 8 , wherein the second set of multiplexers is coupled to the first set of multiplexers via a multiplexer bus.
12. The system of claim 11 , wherein the second set of transceivers is coupled to the second set of multiplexers.
13. The system of claim 8 , wherein the interconnect bridge comprises a 2.5D interface.
14. The system of claim 8 , comprising a multiplexer controller that couple the subset of transceivers based on a configuration of the protocol circuitry.
15. The system of claim 8 , wherein the protocol circuitry comprises Peripheral Component Interconnect Express (PCIe) circuitry that implements a PCIe protocol.
16. The system of claim 8 , wherein the protocol circuitry comprises at least in part hardened logic.
17. A method for operation of transceiver circuitry, the method comprising:
detecting a bandwidth of a data link established using protocol circuitry of the transceiver circuitry that implements a communication protocol, wherein the protocol circuitry is directly coupled to a first channel interface of the transceiver circuitry and a first transceiver of the first transceiver circuitry via a first multiplexer;
determining a number of transceivers to be assigned to the protocol circuitry based on the detected bandwidth of the data link;
determine that the first transceiver is unassigned to the protocol circuitry based on the determination of the number of transceivers to be assigned to the protocol circuitry; and
coupling a second channel interface of the transceiver circuitry to the first transceiver via a second multiplexer that is directly coupled to the first multiplexer and to the second channel interface.
18. The method of claim 17 , wherein coupling the second channel interface of the transceiver circuitry to the first transceiver comprises:
configuring the second multiplexer of the transceiver circuitry coupled to the second channel interface of the transceiver circuitry; and
configuring the first multiplexer of the transceiver circuitry coupled to the first transceiver and to the second multiplexer.
19. The method of claim 17 , wherein detecting the bandwidth of the data link is performed during an initial configuration of the data link.