Asymmetrical Memory Circuits And Methods
A memory circuit includes first and second inverters that are cross coupled. The first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit. The first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.
1 . A memory circuit comprising:
first and second inverters that are cross coupled, wherein the first inverter is configured to provide a first drive current from a first supply line to store a first logic state in the memory circuit, and wherein the first drive current is larger than a second drive current that the second inverter is configured to provide from the first supply line to store a second logic state in the memory circuit.
2 . The memory circuit of claim 1 , wherein the first inverter comprises first and second transistors coupled in parallel between the first supply line and an input of the second inverter.
3 . The memory circuit of claim 2 , wherein the first inverter further comprises a third transistor coupled between the second transistor and the first supply line.
4 . The memory circuit of claim 1 , wherein the first inverter comprises a first transistor coupled to the first supply line, wherein the second inverter comprises a second transistor coupled to the first supply line, and wherein the first transistor has a larger size than the second transistor.
5 . The memory circuit of claim 4 , wherein the first transistor has at least two times a channel width-to-length ratio of the second transistor.
6 . The memory circuit of claim 1 , wherein the second inverter is configured to provide a third drive current to a second supply line to store the first logic state in the memory circuit, and wherein the third drive current is larger than a fourth drive current that the first inverter is configured to provide to the second supply line to store the second logic state in the memory circuit.
7 . The memory circuit of claim 1 , wherein the first drive current is at least two times the second drive current.
8 . The memory circuit of claim 1 , wherein the memory circuit is a static random access memory circuit.
9 . The memory circuit of claim 1 further comprising:
a first pass transistor coupled between a first bit line and the first and the second inverters; and
a second pass transistor coupled between a second bit line and the first and the second inverters.
10 . A method for storing data in a memory circuit, the method comprising:
providing a first drive current through a first inverter from a first supply line to store a first logic state in the memory circuit; and
providing a second drive current through a second inverter from the first supply line to store a second logic state in the memory circuit, wherein the first drive current is larger than the second drive current.
11 . The method of claim 10 , wherein providing the first drive current through the first inverter comprises providing a first portion of the first drive current through a first transistor in the first inverter, and providing a second portion of the first drive current through a second transistor in the first inverter.
12 . The method of claim 11 , wherein providing the second portion of the first drive current through the second transistor comprises providing the second portion of the first drive current through the second transistor and a third transistor coupled in series with the second transistor.
13 . The method of claim 10 , wherein providing the first drive current through the first inverter comprises providing the first drive current through a first transistor in the first inverter, wherein providing the second drive current through the second inverter comprises providing the second drive current through a second transistor in the second inverter, and wherein the first transistor is larger than the second transistor.
14 . The method of claim 10 further comprising:
providing a third drive current through the second inverter to a second supply line to store the first logic state in the memory circuit; and
providing a fourth drive current through the first inverter to the second supply line to store the second logic state in the memory circuit, wherein the third drive current is larger than the fourth drive current.
15 . The method of claim 10 , wherein the first drive current is at least 1 . 5 times the second drive current.
16 . A storage circuit comprising:
first and second inverters, wherein the first inverter comprises one or more first transistors coupled between a first supply line and a first node in the storage circuit, wherein the second inverter comprises a second transistor coupled between the first supply line and a second node in the storage circuit, and wherein the one or more first transistors have a larger size than the second transistor.
17 . The storage circuit of claim 16 , wherein the one or more first transistors comprise at least two of the first transistors coupled in parallel.
18 . The storage circuit of claim 16 , wherein the first inverter further comprises a third transistor coupled between a second supply line and the first node, wherein the second inverter further comprises one or more fourth transistors coupled between the second supply line and the second node, and wherein the one or more fourth transistors have a larger size than the third transistor.
19 . The storage circuit of claim 16 , wherein a single one of the one or more first transistors has a larger size than the second transistor.
20 . The storage circuit of claim 16 , wherein the first and the second inverters are cross coupled.