IP Library Patent Application 18070361
Patent Application
App. No. 18/070,361

Circuit Systems And Methods Using Spacer Dies

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Quick Facts
Patent No.
US None
App. No.
18/070,361
Abstract

An integrated circuit package includes a first integrated circuit die, a spacer die coupled in the integrated circuit package in a location designed to house a second integrated circuit die, and a package substrate coupled to the first integrated circuit die and to the spacer die.

Claims (34)

1 . An integrated circuit package comprising:

a first integrated circuit die; and

a first spacer die coupled in the integrated circuit package in a first location designed to house a second integrated circuit die.

2 . The integrated circuit package of claim 1 further comprising:

a package substrate coupled to the first integrated circuit die and to the first spacer die.

3 . The integrated circuit package of claim 1 further comprising:

a second spacer die coupled in the integrated circuit package in a second location designed to house a third integrated circuit die.

4 . The integrated circuit package of claim 1 , wherein the first spacer die is an open circuit die that blocks leakage current.

5 . The integrated circuit package of claim 1 , wherein the first integrated circuit die comprises a processing integrated circuit.

6 . The integrated circuit package of claim 1 further comprising:

a third integrated circuit die coupled to the first integrated circuit die.

7 . The integrated circuit package of claim 6 , wherein the third integrated circuit die comprises a first transceiver integrated circuit, and wherein the first spacer die is coupled in the integrated circuit package in the first location that is designed to house a second transceiver integrated circuit.

8 . The integrated circuit package of claim 1 , wherein the first spacer die has a same size as the second integrated circuit die.

9 . A method for forming an integrated circuit package, the method comprising:

coupling a first integrated circuit die in the integrated circuit package; and

coupling a first spacer die in the integrated circuit package in a first location designed to house a second integrated circuit die.

10 . The method of claim 9 , wherein coupling the first integrated circuit die in the integrated circuit package and coupling the first spacer die in the integrated circuit package further comprise coupling the first integrated circuit die and the first spacer die to a package substrate.

11 . The method of claim 9 further comprising:

coupling a second spacer die in the integrated circuit package in a second location designed to house a third integrated circuit die.

12 . The method of claim 11 , wherein each of the first and the second spacer dies is an open circuit die that lacks active circuits.

13 . The method of claim 9 further comprising:

coupling a third integrated circuit die to the first integrated circuit die in the integrated circuit package.

14 . The method of claim 9 , wherein the first integrated circuit die comprises a processing integrated circuit, and wherein the first spacer die is coupled in the integrated circuit package in the first location that is designed to house a transceiver integrated circuit.

15 . A circuit system comprising:

a substrate;

a first integrated circuit die coupled to the substrate; and

a first spacer die coupled to the substrate at a first location designed to house a second integrated circuit die.

16 . The circuit system of claim 15 further comprising:

a second spacer die coupled to the substrate at a second location designed to house a third integrated circuit die.

17 . The circuit system of claim 15 , wherein the substrate is a package substrate, and wherein the circuit system is an integrated circuit package.

18 . The circuit system of claim 15 further comprising:

a third integrated circuit die coupled to the substrate.

19 . The circuit system of claim 15 , wherein the first spacer die is an open circuit die that blocks leakage current through the first spacer die.

20 . The circuit system of claim 15 , wherein the first spacer die has a same footprint over the substrate as the second integrated circuit die.

Assignments (3)
SECURITY INTEREST Recorded Sep 12, 2025
From: ALTERA CORPORATION
To: BARCLAYS BANK PLC, AS COLLATERAL AGENT
Reel/Frame 073431/0309 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 19, 2024
From: INTEL CORPORATION
To: ALTERA CORPORATION
Reel/Frame 066353/0886 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Nov 28, 2022
From: YONG, SHEUE FEN; SRINIVASAN, ARCHANNA; BAKER, GRAHAM; TEH, PHEAK TI
To: INTEL CORPORATION
Reel/Frame 061896/0983 →